From: Jiri Slaby <jirislaby@kernel.org>
To: Andrew Jeffery <andrew@aj.id.au>, linux-serial@vger.kernel.org
Cc: gregkh@linuxfoundation.org, joel@jms.id.au,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org,
jenmin_yuan@aspeedtech.com, ryan_chen@aspeedtech.com,
miltonm@us.ibm.com
Subject: Re: [PATCH v2 2/2] serial: 8250: Use BIT(x) for UART_{CAP,BUG}_*
Date: Wed, 19 May 2021 08:14:16 +0200 [thread overview]
Message-ID: <56ec152a-560b-1eed-97e2-c12e4fed171a@kernel.org> (raw)
In-Reply-To: <20210519000704.3661773-3-andrew@aj.id.au>
On 19. 05. 21, 2:07, Andrew Jeffery wrote:
> BIT(x) improves readability and safety with respect to shifts.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> drivers/tty/serial/8250/8250.h | 33 +++++++++++++++++----------------
> 1 file changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
> index 34aa2714f3c9..4fbf1088fad8 100644
> --- a/drivers/tty/serial/8250/8250.h
> +++ b/drivers/tty/serial/8250/8250.h
> @@ -7,6 +7,7 @@
> * Copyright (C) 2001 Russell King.
> */
>
> +#include <linux/bitops.h>
> #include <linux/serial_8250.h>
> #include <linux/serial_reg.h>
> #include <linux/dmaengine.h>
> @@ -70,25 +71,25 @@ struct serial8250_config {
> unsigned int flags;
> };
>
> -#define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
> -#define UART_CAP_EFR (1 << 9) /* UART has EFR */
> -#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
> -#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
> -#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
> -#define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
> -#define UART_CAP_HFIFO (1 << 14) /* UART has a "hidden" FIFO */
> -#define UART_CAP_RPM (1 << 15) /* Runtime PM is active while idle */
> -#define UART_CAP_IRDA (1 << 16) /* UART supports IrDA line discipline */
> -#define UART_CAP_MINI (1 << 17) /* Mini UART on BCM283X family lacks:
> +#define UART_CAP_FIFO BIT(8) /* UART has FIFO */
> +#define UART_CAP_EFR BIT(9) /* UART has EFR */
> +#define UART_CAP_SLEEP BIT(10) /* UART has IER sleep */
Perfect, except the include: BIT is not defined in bitops.h, but in
bits.h (which includes vdso/bits.h). In fact, bitops.h includes bits.h
too, but it's superfluous to include all those bitops.
thanks,
--
--
js
suse labs
next prev parent reply other threads:[~2021-05-19 6:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-19 0:07 [PATCH v2 0/2] serial: 8250: Mitigate Tx stall risk for Aspeed VUARTs Andrew Jeffery
2021-05-19 0:07 ` [PATCH v2 1/2] serial: 8250: Add UART_BUG_TXRACE workaround for Aspeed VUART Andrew Jeffery
2021-05-19 0:58 ` Joel Stanley
2021-05-19 4:58 ` Andrew Jeffery
2021-05-19 6:10 ` Jiri Slaby
2021-05-19 0:07 ` [PATCH v2 2/2] serial: 8250: Use BIT(x) for UART_{CAP,BUG}_* Andrew Jeffery
2021-05-19 6:14 ` Jiri Slaby [this message]
2021-05-19 6:27 ` Andrew Jeffery
2021-05-19 6:32 ` Jiri Slaby
2021-05-19 6:35 ` Andrew Jeffery
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