From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753472AbcDSLBA (ORCPT ); Tue, 19 Apr 2016 07:01:00 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:59674 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752979AbcDSLA6 (ORCPT ); Tue, 19 Apr 2016 07:00:58 -0400 X-AuditID: cbfee691-f795a6d0000012b5-ec-57160fe73be9 Message-id: <57160FE6.8040401@samsung.com> Date: Tue, 19 Apr 2016 20:00:54 +0900 From: Jaehoon Chung User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-version: 1.0 To: Prabu Thangamuthu , "Ulf Hansson (ulf.hansson@linaro.org)" , Adrian Hunter , Bjorn Helgaas , Andrew Morton , "David S. Miller" , Greg Kroah-Hartman , Kalle Valo , Mauro Carvalho Chehab , Guenter Roeck , Jiri Slaby , Chaotian Jing , Andrei Pistirica , Ben Hutchings , Joshua Henderson , Ludovic Desroches Cc: Manjunath M Bettegowda , "linux-mmc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , CPGS Subject: Re: [PATCH v2] mmc: sdhci-pci: add Support of Synopsys DWC_MSHC IP References: <705D14B1C7978B40A723277C067CEDE2010A4B0FD7@IN01WEMBXB.internal.synopsys.com> In-reply-to: <705D14B1C7978B40A723277C067CEDE2010A4B0FD7@IN01WEMBXB.internal.synopsys.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprGKsWRmVeSWpSXmKPExsWyRsSkWPc5v1i4wdMH3BYnn6xhs5izHkjM 2zKZ3eLGzn+sFkuaMiyu3ZrPZvHykKbFnPMtLBbNi9ezWbyeuYLZYsqGD0wWi1YuZLO4vGsO m8WR//2MFk8WnmGyODQz2WLF7LlsFqufVVhM2Hqc1eL42nAHEY8Fv7ayeFzu62XyePZyMpPH lpU3mTwWbCr1WLznJZPHnWt72DxOzPjN4rF/7hp2j5aT+1k87vxYyuixpf8uu8fO7w3sHn1b VjF6rN9ylcVjy/7PjAGCUVw2Kak5mWWpRfp2CVwZT+a9Zit4385Y8frmL9YGxj0ZXYwcHBIC JhIz+kq6GDmBTDGJC/fWs3UxcnEICaxglDi96gYTRMJEouXse3aIxCxGiXMvH0A5Dxglbs1r YgSp4hXQkuhq+sYKYrMIqEo8mz2PHcRmE9CR2P7tONgkUYEwiQfr9rJC1AtK/Jh8jwVkkIjA I1aJDf9WsIAkmAXOMkr8upUOYgsLeEvsXjELbIGQQLREz7KHYEM5BWIk2nd8YgF5gVlAT+L+ RS2IVnmJzWveMoPMlBBo5pQ4tP45M8RBAhLfJh9igXhZVmLTAWaIzyQlDq64wTKBUWwWkpNm IUydhWTqAkbmVYyiqQXJBcVJ6UWmesWJucWleel6yfm5mxiByeX0v2cTdzDeP2B9iFGAg1GJ h3dlkWi4EGtiWXFl7iFGU6AjJjJLiSbnA1NYXkm8obGZkYWpiamxkbmlmZI4r470z2AhgfTE ktTs1NSC1KL4otKc1OJDjEwcnFINjOe+vbLv6T7/yc7HyqNwecz0rqU7VFVy3B3aGSRvTqj7 0WjtP5vJjOOE04ms5VFrj3FW7RPJ09N7kdq0bF9dtUtY/sbqS5Z+ezcoqe9cdtzB7u+i6FZX cYNLAVfeajzMWtn9495PIamf3wu567bzvWjRXZKVkSyfkbrHNEQxZ/KVm3w8G2UuKLEUZyQa ajEXFScCAPOBSsspAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCKsWRmVeSWpSXmKPExsVy+t9jQd3n/GLhBp+XM1mcfLKGzWLOeiAx b8tkdosbO/+xWixpyrC4dms+m8XLQ5oWc863sFg0L17PZvF65gpmiykbPjBZLFq5kM3i8q45 bBZH/vczWjxZeIbJ4tDMZIsVs+eyWax+VmExYetxVovja8MdRDwW/NrK4nG5r5fJ49nLyUwe W1beZPJYsKnUY/Gel0wed67tYfM4MeM3i8f+uWvYPVpO7mfxuPNjKaPHlv677B47vzewe/Rt WcXosX7LVRaPLfs/MwYIRjUw2mSkJqakFimk5iXnp2TmpdsqeQfHO8ebmhkY6hpaWpgrKeQl 5qbaKrn4BOi6ZeYAva6kUJaYUwoUCkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzHgy 7zVbwft2xorXN3+xNjDuyehi5OSQEDCRaDn7nh3CFpO4cG89WxcjF4eQwCxGiXMvH7BDOA8Y JW7Na2IEqeIV0JLoavrGCmKzCKhKPJs9D6ybTUBHYvu340wgtqhAmMSDdXtZIeoFJX5MvscC MkhE4BGrxIZ/K1hAEswCZxklft1KB7GFBbwldq+YBbZASCBaomfZQ7ChnAIxEu07PgHVcwDV 60ncv6gF0SovsXnNW+YJjEBnIqyYhVA1C0nVAkbmVYwSqQXJBcVJ6blGeanlesWJucWleel6 yfm5mxjBKeyZ9A7Gw7vcDzEKcDAq8fCuKBINF2JNLCuuzD3EKMHBrCTCywRMgEK8KYmVValF +fFFpTmpxYcYTYFhMJFZSjQ5H5he80riDY1NzIwsjcwNLYyMzZXEeR//XxcmJJCeWJKanZpa kFoE08fEwSnVwDi/Omp/Vr3X/rCUVwwd337Hli/oYfg/OYXpqabAhNxnv1+8Cdqwv+tbbvO9 wDk3E+Lifvld++wT4auxar3H+crUVf88tm+9b8fAkP/9ydYTk1p7lrBkO1+7ZMh0+FRovJ5V +dF0q/k/bc5sDu6yTlpxwF789Yl+zd1K+0XXXCzdEMMvuNAgIVqJpTgj0VCLuag4EQCfPhJ7 dwMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/19/2016 04:18 PM, Prabu Thangamuthu wrote: > Synopsys DWC_MSHC is compliant with SD Host Specifications. This patch > is to support DWC_MSHC controller on PCI interface. There is dwmmc controller for Synopsys DWC_MSHC. According to commit message, dwmmc controller also is compliant with SD host specifications. I think it's enough to use "sdhci-dwc".(To prevent confusion.) > > Signed-off-by: Prabu Thangamuthu > --- > Change log v2: > -Removed Synopsys specific PCI device ID's from pci_ids.h. > -Updated the PCI device ID's in sdhci-pci-core.c. > > MAINTAINERS | 7 + > drivers/mmc/host/Makefile | 3 +- > drivers/mmc/host/sdhci-dwc-mshc-pci.c | 298 ++++++++++++++++++++++++++++++++++ > drivers/mmc/host/sdhci-dwc-mshc-pci.h | 58 +++++++ > drivers/mmc/host/sdhci-pci-core.c | 14 ++ > 5 files changed, 379 insertions(+), 1 deletion(-) > create mode 100644 drivers/mmc/host/sdhci-dwc-mshc-pci.c > create mode 100644 drivers/mmc/host/sdhci-dwc-mshc-pci.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 1d5b4be..b260b97 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -9751,6 +9751,13 @@ S: Maintained > F: include/linux/mmc/dw_mmc.h > F: drivers/mmc/host/dw_mmc* > > +SYNOPSYS SDHCI COMPLIANT DWC MSHC DRIVER > +M: Prabu Thangamuthu > +M: Manjunath M B > +L: linux-mmc@vger.kernel.org > +S: Maintained > +F: drivers/mmc/host/sdhci-dwc-mshc* > + > SYSTEM TRACE MODULE CLASS > M: Alexander Shishkin > S: Maintained > diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile > index af918d2..1d2a3cf 100644 > --- a/drivers/mmc/host/Makefile > +++ b/drivers/mmc/host/Makefile > @@ -9,7 +9,8 @@ obj-$(CONFIG_MMC_MXC) += mxcmmc.o > obj-$(CONFIG_MMC_MXS) += mxs-mmc.o > obj-$(CONFIG_MMC_SDHCI) += sdhci.o > obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o > -sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o > +sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o \ > + sdhci-dwc-mshc-pci.o how about using sdhci-pci-XXX? > obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o > obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o > obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o > diff --git a/drivers/mmc/host/sdhci-dwc-mshc-pci.c b/drivers/mmc/host/sdhci-dwc-mshc-pci.c > new file mode 100644 > index 0000000..e934af4 > --- /dev/null > +++ b/drivers/mmc/host/sdhci-dwc-mshc-pci.c > @@ -0,0 +1,298 @@ > +/* > + * Copyright (C) 2016 Synopsys, Inc. > + * > + * Author: Manjunath M B > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > + > +#include "sdhci.h" > +#include "sdhci-pci.h" > +#include "sdhci-dwc-mshc-pci.h" > + > +/*****************************************************************************\ > + * * > + * Hardware specific clock handling * > + * * > +\*****************************************************************************/ > +static const struct sdhci_ops *sdhci_ops; /* Low level hw interface */ > + > +static void sdhci_set_clock_snps(struct sdhci_host *host, > + unsigned int clock) > +{ > + int div = 0; > + int mul = 0; > + int div_val = 0; > + int mul_val = 0; > + int mul_div_val = 0; > + int reg = 0; > + u16 clk = 0; > + u32 vendor_ptr; > + unsigned long timeout; > + u32 tx_clk_phase_val = SDHC_DEF_TX_CLK_PH_VAL; > + u32 rx_clk_phase_val = SDHC_DEF_RX_CLK_PH_VAL; > + > + /* DWC MSHC Specific clock settings */ I think this comment don't need..because this file already is IP specific. > + > + /* if clock is less than 25MHz, divided clock is used. > + * For divided clock, we can use the standard sdhci_set_clock(). > + * For clock above 25MHz, DRP clock is used > + * Here, we cannot use sdhci_set_clock(), we need to program > + * TX RX CLOCK DCM DRP for appropriate clock > + */ > + > + vendor_ptr = sdhci_readw(host, SDHCI_UHS2_VENDOR); > + > + if (clock <= 25000000) { > + /* Then call generic set_clock */ > + sdhci_ops->set_clock(host, clock); > + } else { > + > + host->mmc->actual_clock = 0; > + > + /* Select un-phase shifted clock before reset Tx Tuning DCM*/ > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg &= ~SDHC_TX_CLK_SEL_TUNED; > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); > + mdelay(10); > + > + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); > + > + if (clock == 0) > + return; Why return here? Can this locate above? > + > + /* Lets chose the Mulitplier value to be 0x2 */ > + mul = 0x2; > + for (div = 1; div <= 32; div++) { > + if (((host->max_clk * mul) / div) > + <= clock) > + break; > + } > + /* > + * Set Programmable Clock Mode in the Clock > + * Control register. > + */ > + div_val = div - 1; > + mul_val = mul - 1; > + > + host->mmc->actual_clock = (host->max_clk * mul) / div; > + /* Program the DCM DRP */ > + /* Step 1: Assert DCM Reset */ I think more readable that you write the all steps on here. /* * Step1 :... * Step2 :... > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg = reg | SDHC_CARD_TX_CLK_DCM_RST; reg |= SDHC_CARD_... > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); > + > + /* Step 2: Program the mul and div values in DRP */ > + mul_div_val = (mul_val << 8) | div_val; > + sdhci_writew(host, mul_div_val, TXRX_CLK_DCM_MUL_DIV_DRP); > + > + /* Step 3: issue a dummy read from DRP base 0x00 as per > + * www.xilinx.com/support/documentation/user_guides/ug191.pdf > + */ > + reg = sdhci_readw(host, TXRX_CLK_DCM_DRP_BASE_51); This code is workaroud for issue? > + > + /* Step 4: De-Assert reset to DCM */ > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg &= ~SDHC_CARD_TX_CLK_DCM_RST; > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); > + > + clk |= SDHCI_PROG_CLOCK_MODE | SDHCI_CLOCK_INT_EN; > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > + > + /* Wait max 20 ms */ > + timeout = 20; > + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) > + & SDHCI_CLOCK_INT_STABLE)) { > + if (timeout == 0) { > + pr_err("%s: Internal clock never stabilised\n", > + mmc_hostname(host->mmc)); > + return; > + } > + timeout--; > + mdelay(1); > + } > + > + clk |= SDHCI_CLOCK_CARD_EN; > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > + > + /* For some bit-files we may have to do phase shifting for > + * Tx Clock; Let's do it here > + */ > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg = reg | SDHC_TUNING_TX_CLK_DCM_RST; Ditto. > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); > + mdelay(10); > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg &= ~SDHC_TUNING_TX_CLK_DCM_RST; > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); > + > + /* Select working phase value if clock is <= 50MHz */ > + if (clock <= 50000000) { > + /*Change the Phase value here */ > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg = reg | (SDHC_TUNING_TX_CLK_SEL_MASK & > + (tx_clk_phase_val << SDHC_TUNING_TX_CLK_SEL_SHIFT)); > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); > + mdelay(10); > + > + /* Program to select phase shifted clock */ > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg = reg | SDHC_TX_CLK_SEL_TUNED; > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); > + mdelay(10); > + } > + > + /* This Clock might have affected the RX CLOCK DCM > + * used for Phase control; Reset this DCM for proper clock > + */ > + > + /* Program the DCM DRP */ > + /* Step 1: Reset the DCM */ > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg = reg | SDHC_TUNING_RX_CLK_DCM_RST; > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); > + mdelay(10); > + /* Step 2: De-Assert reset to DCM */ > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg &= ~SDHC_TUNING_RX_CLK_DCM_RST; > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); Can these codes reuse? If clock is upper than 50MHz, then only this code is running twice..is it correct? > + > + /* For 50Mhz, tuning is not possible.. Lets fix the sampling > + * Phase of Rx Clock here > + */ > + if (clock <= 50000000) { > + /*Change the Phase value here */ > + reg = sdhci_readl(host, (SDHC_DBOUNCE + vendor_ptr)); > + reg &= ~SDHC_TUNING_RX_CLK_SEL_MASK; > + reg = reg | (SDHC_TUNING_RX_CLK_SEL_MASK & > + rx_clk_phase_val); > + sdhci_writew(host, reg, (SDHC_DBOUNCE + vendor_ptr)); > + } > + mdelay(10); > + } > +} > + > +static int sdhci_pci_enable_dma_snps(struct sdhci_host *host) > +{ > + /* DWC MSHC Specific Dma Enabling */ Ditto.. this file is already DWC specific. > + > + /* Call generic emable_dma */ > + return sdhci_ops->enable_dma(host); > +} > + > +static void sdhci_pci_set_bus_width_snps(struct sdhci_host *host, int width) > +{ > + /* DWC MSHC Specific Bus Width Setting */ Ditto. > + > + /* Call generic set_bus_width */ > + sdhci_ops->set_bus_width(host, width); > +} > + > +static void sdhci_reset_snps(struct sdhci_host *host, u8 mask) > +{ > + /* DWC MSHC Specific hci reset */ > + > + /* Call generic reset */ > + sdhci_ops->reset(host, mask); > +} > +static void sdhci_set_uhs_signaling_snps(struct sdhci_host *host, > + unsigned int timing) > +{ > + /* DWC MSHC Specific UHS-I Signaling */ > + > + /* Call generic UHS-I signaling */ > + sdhci_ops->set_uhs_signaling(host, timing); > +} > +static void sdhci_pci_hw_reset_snps(struct sdhci_host *host) > +{ > + /* DWC MSHC Specific hw reset */ > + > + /* Call generic hw_reset */ > + if (host->ops && host->ops->hw_reset) Above other host->ops-> didn't check..do you think what's correct? > + sdhci_ops->hw_reset(host); > +} > +static const struct sdhci_ops sdhci_pci_ops_snps = { > + .set_clock = sdhci_set_clock_snps, > + .enable_dma = sdhci_pci_enable_dma_snps, > + .set_bus_width = sdhci_pci_set_bus_width_snps, > + .reset = sdhci_reset_snps, > + .set_uhs_signaling = sdhci_set_uhs_signaling_snps, > + .hw_reset = sdhci_pci_hw_reset_snps, > +}; > + > +static int snps_init_clock(struct sdhci_host *host) > +{ > + int div = 0; > + int mul = 0; > + int div_val = 0; > + int mul_val = 0; > + int mul_div_val = 0; > + int reg = 0; > + u32 vendor_ptr; > + > + vendor_ptr = sdhci_readw(host, SDHCI_UHS2_VENDOR); > + > + /* Configure the BCLK DRP to get 100 MHZ Clock */ > + > + /* To get 100MHz from 100MHz input freq, > + * mul=2 and div=2 > + * Formula: output_clock = (input clock * mul) / div > + */ > + mul = 2; > + div = 2; > + mul_val = mul - 1; > + div_val = div - 1; > + /* Program the DCM DRP */ > + /* Step 1: Reset the DCM */ > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg = reg | SDHC_BCLK_DCM_RST; > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); > + /* Step 2: Program the mul and div values in DRP */ > + mul_div_val = (mul_val << 8) | div_val; > + sdhci_writew(host, mul_div_val, BCLK_DCM_MUL_DIV_DRP); > + /* Step 3: issue a dummy read from DRP base 0x00 as per > + * http://www.xilinx.com/support/documentation/user_guides/ug191.pdf > + */ > + reg = sdhci_readw(host, BCLK_DCM_DRP_BASE_51); > + /* Step 4: De-Assert reset to DCM */ > + /* de assert reset*/ > + reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); > + reg &= ~SDHC_BCLK_DCM_RST; > + sdhci_writew(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); I'm not sure but it seems these codes are also simliar to above codes. If i'm correct, you can reduce the code lines. > + > + /* By Default Clocks to MSHC are off.. > + * Before stack applies reset; we need to turn on the clock > + */ > + sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); > + > + return 0; > + > +} > + > +int sdhci_pci_probe_slot_snps(struct sdhci_pci_slot *slot) > +{ > + int ret = 0; > + struct sdhci_host *host; > + > + host = slot->host; > + sdhci_ops = host->ops; > + host->ops = &sdhci_pci_ops_snps; > + > + /* Board specific clock initialization */ > + ret = snps_init_clock(host); > + return ret; > +} > +EXPORT_SYMBOL_GPL(sdhci_pci_probe_slot_snps); > diff --git a/drivers/mmc/host/sdhci-dwc-mshc-pci.h b/drivers/mmc/host/sdhci-dwc-mshc-pci.h > new file mode 100644 > index 0000000..1635bf2 > --- /dev/null > +++ b/drivers/mmc/host/sdhci-dwc-mshc-pci.h > @@ -0,0 +1,58 @@ > +/* > + * Copyright (C) 2016 Synopsys, Inc. > + * > + * Author: Manjunath M B > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#ifndef __SDHCI_DWC_MSHC_PCI_H__ > +#define __SDHCI_DWC_MSHC_PCI_H__ > + > +#include "sdhci-pci.h" > + > +#define SDHCI_UHS2_VENDOR 0xE8 > + > +#define DRIVER_NAME "sdhci_snps" What do you use .."snps" or "dwc_mshc"? As i mentioned, i want not to use "*mshc*" in these patches. Best Regards, Jaehoon Chung > +#define SDHC_DEF_TX_CLK_PH_VAL 4 > +#define SDHC_DEF_RX_CLK_PH_VAL 4 > + > +/* Synopsys Vendor Specific Registers */ > +#define SDHC_DBOUNCE 0x08 > +#define SDHC_TUNING_RX_CLK_SEL_MASK 0x000000FF > +#define SDHC_GPIO_OUT 0x34 > +/* HAPS 51 Based implementation */ > +#define SDHC_BCLK_DCM_RST 0x00000001 > +#define SDHC_CARD_TX_CLK_DCM_RST 0x00000002 > +#define SDHC_TUNING_RX_CLK_DCM_RST 0x00000004 > +#define SDHC_TUNING_TX_CLK_DCM_RST 0x00000008 > +#define SDHC_TUNING_TX_CLK_SEL_MASK 0x00000070 > +#define SDHC_TUNING_TX_CLK_SEL_SHIFT 4 > +#define SDHC_TX_CLK_SEL_TUNED 0x00000080 > + > +/* Offset of BCLK DCM DRP Attributes */ > +/* Every attribute is of 16 bit wide */ > +#define BCLK_DCM_DRP_BASE_51 0x1000 > + > +#define BCLK_DCM_MUL_DIV_DRP 0x1050 > +#define MUL_MASK_DRP 0xFF00 > +#define DIV_MASK_DRP 0x00FF > + > +/* Offset of TX and RX CLK DCM DRP */ > +#define TXRX_CLK_DCM_DRP_BASE_51 0x2000 > +#define TXRX_CLK_DCM_MUL_DIV_DRP 0x2050 > + > +int sdhci_pci_probe_snps(struct sdhci_pci_chip *chip); > +int sdhci_pci_probe_slot_snps(struct sdhci_pci_slot *slot); > +int sdhci_pci_resume_snps(struct sdhci_pci_chip *chip); > +int sdhci_pci_suspend_snps(struct sdhci_pci_chip *chip); > + > +#endif > diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c > index 79e1901..bfa3b39 100644 > --- a/drivers/mmc/host/sdhci-pci-core.c > +++ b/drivers/mmc/host/sdhci-pci-core.c > @@ -31,6 +31,7 @@ > #include "sdhci.h" > #include "sdhci-pci.h" > #include "sdhci-pci-o2micro.h" > +#include "sdhci-dwc-mshc-pci.h" > > /*****************************************************************************\ > * * > @@ -70,6 +71,11 @@ static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) > msleep(500); > return 0; > } > +/* Synopsys DWC MSHC Controller based SDHCI-PCI */ > +static const struct sdhci_pci_fixes sdhci_snps = { > + .probe_slot = sdhci_pci_probe_slot_snps, > + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, > +}; > > static const struct sdhci_pci_fixes sdhci_ricoh = { > .probe = ricoh_probe, > @@ -797,6 +803,14 @@ static const struct sdhci_pci_fixes sdhci_amd = { > > static const struct pci_device_id pci_ids[] = { > { > + .vendor = PCI_VENDOR_ID_SYNOPSYS, > + .device = 0xc201, /* Device ID of MSHC EP on Haps51 */ > + .subvendor = PCI_ANY_ID, > + .subdevice = PCI_ANY_ID, > + .driver_data = (kernel_ulong_t)&sdhci_snps, > + }, > + > + { > .vendor = PCI_VENDOR_ID_RICOH, > .device = PCI_DEVICE_ID_RICOH_R5C822, > .subvendor = PCI_ANY_ID, >