From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754145AbcE3Hl1 (ORCPT ); Mon, 30 May 2016 03:41:27 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:16358 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754011AbcE3HlZ (ORCPT ); Mon, 30 May 2016 03:41:25 -0400 X-AuditID: cbfec7f5-f792a6d000001302-1f-574beea1d680 Subject: Re: [PATCH 2/2] ARM: dts: Add async-bridge clock to MFC power domain for Exynos5420 To: Javier Martinez Canillas , linux-kernel@vger.kernel.org References: <1464111662-15336-1-git-send-email-javier@osg.samsung.com> <1464111662-15336-3-git-send-email-javier@osg.samsung.com> Cc: devicetree@vger.kernel.org, Kukjin Kim , Michael Turquette , Marek Szyprowski , Mauro Carvalho Chehab , Shuah Khan , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sylwester Nawrocki , Tomasz Figa , linux-clk@vger.kernel.org, Nicolas Dufresne From: Krzysztof Kozlowski Message-id: <574BEEA0.5020103@samsung.com> Date: Mon, 30 May 2016 09:41:20 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-version: 1.0 In-reply-to: <1464111662-15336-3-git-send-email-javier@osg.samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJIsWRmVeSWpSXmKPExsVy+t/xa7oL33mHGxz6p2kx/8g5Vos3b9cw Wbx+YWjR//g1s8Wmx9dYLT723GO1uLxrDpvFjPP7mCzWHrnLbrH6WYXFxVOuFru+3GOzOPym ndXix5luFoupXz6wWKza9YfRQcDj/Y1Wdo/Lfb1MHjvuLmH02DnrLrvHplWdbB6bl9R7bOkH 8vq2rGL0+LxJLoAzissmJTUnsyy1SN8ugSuja/02toKFAhXfrq9jbmDcxtvFyMkhIWAisfvR MhYIW0ziwr31bF2MXBxCAksZJa5P2coE4TxjlJh+egkbSJWwQJzEzV8rGEFsEYFQiX8XbzNC FDUzSvQfXwvWwSzQwyJxYtVmsCo2AWOJzcshunkFtCTOzHkHto9FQFVi95S3YDWiAhESs7b/ YIKoEZT4MfkeWA2ngLvEo53nmbsYOYCG6kncv6gFEmYWkJfYvOYt8wRGgVlIOmYhVM1CUrWA kXkVo2hqaXJBcVJ6rpFecWJucWleul5yfu4mRkiEfd3BuPSY1SFGAQ5GJR7eAk3vcCHWxLLi ytxDjBIczEoivG8fA4V4UxIrq1KL8uOLSnNSiw8xSnOwKInzztz1PkRIID2xJDU7NbUgtQgm y8TBKdXAeD3WMtXp2mwtt8YkBavX0zce3ej6+WBFO3uLT4PO0z2Lzr5h/Drxctf0PjGPeYGc /hH7rxZuvnW+92jqROGkLJ89sxd69sb4zl3m16S4oizfQjfq1wzOeu+7jsqZex1OB3m03U/r TCn81J1ev+bvsfpI9ek22/efP/x/rZz7srpDztumOhSVKrEUZyQaajEXFScCALqdMpGsAgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/24/2016 07:41 PM, Javier Martinez Canillas wrote: > The MFC IP is also inter-connected by an Async-Bridge so the CLK_ACLK333 > has to be ungated during a power domain switch. Trying to do it when the > clock is gated will fail and lead to an imprecise external abort error > when the driver tries to access the MFC registers with the PD disabled. > > For example, if the s5p-mfc module is removed and the MFC PD turned off: > > [ 186.835606] Power domain power-domain@10044060 disable failed > [ 186.835671] s5p-mfc 11000000.codec: Removing 11000000.codec > [ 186.837670] Power domain power-domain@10044060 disable failed > > And when the module is inserted again: > > [ 2395.176956] s5p_mfc_wait_for_done_dev:34: Interrupt (dev->int_type:0, command:12) timed out > [ 2395.177031] s5p_mfc_init_hw:272: Failed to load firmware > [ 2395.177384] Unhandled fault: imprecise external abort (0x1406) at 0x00000000 > [ 2395.177441] pgd = ec3b4000 > [ 2395.177467] [00000000] *pgd=00000000 > [ 2395.177507] Internal error: : 1406 [#1] PREEMPT SMP ARM > [ 2395.177550] Modules linked in: s5p_mfc mwifiex_sdio mwifiex uvcvideo s5p_jpeg v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig videobuf2_memops videobuf2_v4l2 videobuf2_core v4l2_common videodev media [last unloaded: s5p_mfc] > [ 2395.177774] CPU: 1 PID: 2382 Comm: v4l_id Tainted: G W 4.6.0-rc6-next-20160502-00010-g7730dc64d2c1-dirty #179 > [ 2395.177857] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) > [ 2395.177906] task: ed275500 ti: e6c8c000 task.ti: e6c8c000 > [ 2395.177996] PC is at s5p_mfc_reset+0x1c4/0x284 [s5p_mfc] > [ 2395.178057] LR is at s5p_mfc_reset+0x1a4/0x284 [s5p_mfc] > > This patch fixes this issue by adding the CLK_ACLK333 as an Async-Bridge > clock for the MFC power domain, so the PD configuration works properly. > > Signed-off-by: Javier Martinez Canillas > > --- > > arch/arm/boot/dts/exynos5420.dtsi | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) Thanks, applied. Krzysztof