From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8134BC25B06 for ; Mon, 8 Aug 2022 08:04:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238267AbiHHIET (ORCPT ); Mon, 8 Aug 2022 04:04:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231496AbiHHIER (ORCPT ); Mon, 8 Aug 2022 04:04:17 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C17C413D3F; Mon, 8 Aug 2022 01:04:09 -0700 (PDT) X-UUID: 5e3ad97a77e34191ada0152c7f724a11-20220808 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=rLpQA2HDs6HPyBnCtsxUkBeWCCaY6SEoWDsQLMWSn6E=; b=VnyxvmC2wet1tG9LzRfZZB/QlP00LMJ4f5KHU7soY0SXhxZa3CTGSAkr/N0l7AFxty0mLRFXdX94h9iew3sRF3XSmAhoKSjH49JVsJTu2NX0RGYF2XC/KYfzSO0JkafFHGvfkhzYxXzsdtM1kw45mqlQU12YdHinxe/x8DxZXAU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.9,REQID:d35900d0-85e1-4926-9341-baac68d5a81f,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_H am,ACTION:release,TS:0 X-CID-META: VersionHash:3d8acc9,CLOUDID:f8d90d9c-da39-4e3b-a854-56c7d2111b46,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 5e3ad97a77e34191ada0152c7f724a11-20220808 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1122278036; Mon, 08 Aug 2022 16:04:03 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 8 Aug 2022 16:04:01 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 8 Aug 2022 16:04:01 +0800 Message-ID: <575181dc6cdd1fcf391e840c0fcd5722b954a457.camel@mediatek.com> Subject: Re: [PATCH v16 3/8] drm/mediatek: Add MT8195 Embedded DisplayPort driver From: CK Hu To: Bo-Chen Chen , , , , , , , , , , CC: , , , , , , , , , , , , Date: Mon, 8 Aug 2022 16:04:01 +0800 In-Reply-To: <20220805101459.3386-4-rex-bc.chen@mediatek.com> References: <20220805101459.3386-1-rex-bc.chen@mediatek.com> <20220805101459.3386-4-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Bo-Chen: On Fri, 2022-08-05 at 18:14 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > Signed-off-by: Bo-Chen Chen > Tested-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- [snip] > + > +static enum drm_mode_status > +mtk_dp_bridge_mode_valid(struct drm_bridge *bridge, > + const struct drm_display_info *info, > + const struct drm_display_mode *mode) > +{ > + struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); > + u32 rx_linkrate = (u32)mtk_dp->train_info.link_rate * 27000; > + u32 bpp = info->color_formats & DRM_COLOR_FORMAT_YCBCR422 ? 16 > : 24; > + > + if (rx_linkrate * mtk_dp->train_info.lane_count < mode->clock * > bpp / 8) > + return MODE_CLOCK_HIGH; > + > + if (mode->clock > 600000) If the clock has pass the linkrate and land_count limitation, the clock would be OK because the linkrate and lane_count is trained. Why need to check 600000? Regards, CK > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} > +