From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752594AbcFFMoK (ORCPT ); Mon, 6 Jun 2016 08:44:10 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:10312 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751316AbcFFMoG (ORCPT ); Mon, 6 Jun 2016 08:44:06 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 06 Jun 2016 05:41:51 -0700 Subject: Re: [PATCH V5 7/9] irqchip/gic: Prepare for adding platform driver To: Thomas Gleixner , Jason Cooper , Marc Zyngier References: <1465214023-8299-1-git-send-email-jonathanh@nvidia.com> <1465214023-8299-8-git-send-email-jonathanh@nvidia.com> CC: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Kevin Hilman , Geert Uytterhoeven , Grygorii Strashko , Lars-Peter Clausen , "Linus Walleij" , , , From: Jon Hunter Message-ID: <57556F0F.9030605@nvidia.com> Date: Mon, 6 Jun 2016 13:39:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <1465214023-8299-8-git-send-email-jonathanh@nvidia.com> X-Originating-IP: [10.21.132.106] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL102.nvidia.com (10.26.138.15) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/06/16 12:53, Jon Hunter wrote: > To support GICs that require runtime power management, it is necessary > to add a platform driver, so that the probing of the chip can be > deferred if resources, such as a power-domain, is not yet available. > > To prepare for adding a platform driver: > 1. Drop the __init section from the gic_dist_config() so this can be > re-used by the platform driver. > 2. Add prototypes for functions required by the platform driver to the > GIC header file so they can be re-used. > > Signed-off-by: Jon Hunter > --- > drivers/irqchip/irq-gic-common.c | 4 ++-- > drivers/irqchip/irq-gic.c | 15 ++++++++------- > include/linux/irqchip/arm-gic.h | 5 +++++ > 3 files changed, 15 insertions(+), 9 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c > index 89e7423f0ebb..9ae71804b5dd 100644 > --- a/drivers/irqchip/irq-gic-common.c > +++ b/drivers/irqchip/irq-gic-common.c > @@ -90,8 +90,8 @@ int gic_configure_irq(unsigned int irq, unsigned int type, > return ret; > } > > -void __init gic_dist_config(void __iomem *base, int gic_irqs, > - void (*sync_access)(void)) > +void gic_dist_config(void __iomem *base, int gic_irqs, > + void (*sync_access)(void)) > { > unsigned int i; > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > index 94eab6e23124..3d3ab9045244 100644 > --- a/drivers/irqchip/irq-gic.c > +++ b/drivers/irqchip/irq-gic.c > @@ -449,7 +449,7 @@ static void gic_cpu_if_up(struct gic_chip_data *gic) > } > > > -static void __init gic_dist_init(struct gic_chip_data *gic) > +static void gic_dist_init(struct gic_chip_data *gic) > { > unsigned int i; > u32 cpumask; > @@ -535,7 +535,7 @@ int gic_cpu_if_down(unsigned int gic_nr) > * this function, no interrupts will be delivered by the GIC, and another > * platform-specific wakeup source must be enabled. > */ > -static void gic_dist_save(struct gic_chip_data *gic) > +void gic_dist_save(struct gic_chip_data *gic) > { > unsigned int gic_irqs; > void __iomem *dist_base; > @@ -574,7 +574,7 @@ static void gic_dist_save(struct gic_chip_data *gic) > * handled normally, but any edge interrupts that occured will not be seen by > * the GIC and need to be handled by the platform-specific wakeup source. > */ > -static void gic_dist_restore(struct gic_chip_data *gic) > +void gic_dist_restore(struct gic_chip_data *gic) > { > unsigned int gic_irqs; > unsigned int i; > @@ -620,7 +620,7 @@ static void gic_dist_restore(struct gic_chip_data *gic) > writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); > } > > -static void gic_cpu_save(struct gic_chip_data *gic) > +void gic_cpu_save(struct gic_chip_data *gic) > { > int i; > u32 *ptr; > @@ -650,7 +650,7 @@ static void gic_cpu_save(struct gic_chip_data *gic) > > } > > -static void gic_cpu_restore(struct gic_chip_data *gic) > +void gic_cpu_restore(struct gic_chip_data *gic) > { > int i; > u32 *ptr; > @@ -727,7 +727,7 @@ static struct notifier_block gic_notifier_block = { > .notifier_call = gic_notifier, > }; > > -static int __init gic_pm_init(struct gic_chip_data *gic) > +static int gic_pm_init(struct gic_chip_data *gic) > { > gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, > sizeof(u32)); > @@ -757,7 +757,7 @@ free_ppi_enable: > return -ENOMEM; > } > #else > -static int __init gic_pm_init(struct gic_chip_data *gic) > +static int gic_pm_init(struct gic_chip_data *gic) > { > return 0; > } > @@ -1179,6 +1179,7 @@ static int __init __gic_init_bases(struct gic_chip_data *gic, > set_smp_cross_call(gic_raise_softirq); > register_cpu_notifier(&gic_cpu_notifier); > #endif > + Not sure where this extra line came from but shouldn't be here. Marc let me know if you want me to resend. Jon -- nvpublic