From: Suzuki K Poulose <Suzuki.Poulose@arm.com>
To: Andre Przywara <andre.przywara@arm.com>,
Will Deacon <will.deacon@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 6/6] arm64: trap userspace "dc cvau" cache operation on errata-affected core
Date: Fri, 17 Jun 2016 18:25:02 +0100 [thread overview]
Message-ID: <5764326E.1080702@arm.com> (raw)
In-Reply-To: <c5d47238-6391-8468-b9d7-6a28e82a3edc@arm.com>
On 17/06/16 18:20, Andre Przywara wrote:
> Hi Suzuki,
>
> thanks for having a look!
>
> On 14/06/16 17:16, Suzuki K Poulose wrote:
>> On 09/05/16 17:49, Andre Przywara wrote:
>>> The ARM errata 819472, 826319, 827319 and 824069 for affected
>>> Cortex-A53 cores demand to promote "dc cvau" instructions to
>>> "dc civac". Since we allow userspace to also emit those instructions,
>>> we should make sure that "dc cvau" gets promoted there too.
>>> So lets grasp the nettle here and actually trap every userland cache
>>> maintenance instruction once we detect at least one affected core in
>>> the system.
__user_cache_maint("dc civac", address, ret);
>>> + break;
>>> + case 10: /* DC CVAC, gets promoted */
>>> + __user_cache_maint("dc civac", address, ret);
>>> + break;
>>> + case 14: /* DC CIVAC */
>>> + __user_cache_maint("dc civac", address, ret);
>>> + break;
>>> + case 5: /* IC IVAU */
>>> + __user_cache_maint("ic ivau", address, ret);
>>> + break;
>>> + default:
>>> + force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
>>> + return;
>>> + }
>>> + } else {
>>> + force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
>>> + return;
>>
>> Correct me if I am wrong, I think we should handle DC ZVA and emulate
>> the same ?
>> Thats the only EL0 accessible instruction we don't handle above.
>
> Mmmh, but why should we care?
> 1) DC ZVA is not trapped by setting SCTLR.UCI - instead it has its own
> bit (SCTLR.DZE).
You are right. I was thinking that UCI traps all DC operations. It only
traps DC CVAU, DC CIVAC, DC CVAC, and IC IVAU.
Cheers
Suzuki
next prev parent reply other threads:[~2016-06-17 17:25 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-09 16:49 [PATCH 0/6] arm64: Extend Cortex-A53 errata workaround Andre Przywara
2016-05-09 16:49 ` [PATCH 1/6] arm64: alternatives: drop enable parameter from _else and _endif macro Andre Przywara
2016-06-23 17:17 ` Catalin Marinas
2016-05-09 16:49 ` [PATCH 2/6] arm64: fix "dc cvau" cache operation on errata-affected core Andre Przywara
2016-05-09 16:49 ` [PATCH 3/6] arm64: include alternative handling in dcache_by_line_op Andre Przywara
2016-06-24 15:32 ` Catalin Marinas
2016-05-09 16:49 ` [PATCH 4/6] arm64: errata: Calling enable functions for CPU errata too Andre Przywara
2016-06-10 15:31 ` Suzuki K Poulose
2016-06-24 15:34 ` Catalin Marinas
2016-05-09 16:49 ` [PATCH 5/6] arm64: consolidate signal injection on emulation errors Andre Przywara
2016-05-09 16:49 ` [PATCH 6/6] arm64: trap userspace "dc cvau" cache operation on errata-affected core Andre Przywara
2016-06-14 16:16 ` Suzuki K Poulose
2016-06-17 17:20 ` Andre Przywara
2016-06-17 17:25 ` Suzuki K Poulose [this message]
2016-06-24 16:25 ` Catalin Marinas
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