From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752195AbcFVDyL (ORCPT ); Tue, 21 Jun 2016 23:54:11 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:33132 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751572AbcFVDyI (ORCPT ); Tue, 21 Jun 2016 23:54:08 -0400 Subject: Re: [PATCH v10 08/22] IB/hns: Add icm support To: References: <1466087730-54856-1-git-send-email-oulijun@huawei.com> <1466087730-54856-9-git-send-email-oulijun@huawei.com> <20160617095834.GA5408@leon.nu> <57677314.70909@huawei.com> <20160620060614.GC1172@leon.nu> <5767A004.4060808@huawei.com> <20160620092719.GE1172@leon.nu> <5767BBDF.6010309@huawei.com> <20160620130422.GA4526@leon.nu> <5768C493.6000300@huawei.com> <20160621115554.GB9762@leon.nu> CC: Lijun Ou , , , , , , , , , , , , , , , , , , From: "Wei Hu (Xavier)" Message-ID: <576A0BAD.1070803@huawei.com> Date: Wed, 22 Jun 2016 11:53:17 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <20160621115554.GB9762@leon.nu> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.57.115.113] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.576A0BBE.00BB,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 1df9074bce48a2368d62f0ba3ee1fe9a Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2016/6/21 19:55, Leon Romanovsky wrote: > On Tue, Jun 21, 2016 at 12:37:39PM +0800, Wei Hu (Xavier) wrote: >> >> On 2016/6/20 21:04, Leon Romanovsky wrote: >>> On Mon, Jun 20, 2016 at 05:48:15PM +0800, Wei Hu (Xavier) wrote: >>>> On 2016/6/20 17:27, Leon Romanovsky wrote: >>>>> On Mon, Jun 20, 2016 at 03:49:24PM +0800, Wei Hu (Xavier) wrote: >>>>>> On 2016/6/20 14:06, Leon Romanovsky wrote: >>>>>>> On Mon, Jun 20, 2016 at 12:37:40PM +0800, Wei Hu (Xavier) wrote: >>>>>>>> On 2016/6/17 17:58, Leon Romanovsky wrote: >>>>>>>>> On Thu, Jun 16, 2016 at 10:35:16PM +0800, Lijun Ou wrote: >>>>>>>>>> This patch mainly added icm support for RoCE. It initializes icm >>>>>>>>>> which managers the relative memory blocks for RoCE. The data >>>>>>>>>> structures of RoCE will be located in it. For example, CQ table, >>>>>>>>>> QP table and MTPT table so on. >>>>>>>>>> >>>>>>>>>> Signed-off-by: Wei Hu >>>>>>>>>> Signed-off-by: Nenglong Zhao >>>>>>>>>> Signed-off-by: Lijun Ou >>>>>>>>>> --- >>>>>>>>> <...> >>>>>>>>> >>>>>>>>>> + >>>>>>> Another question which you didn't answer [1]. >>>>>>> >>>>>>> "I wonder if you have the same needs for ICM as it is in mlx4 device. >>>>>>> Do you have firmware?" >>>>>>> >>>>>>> [1] http://marc.info/?l=linux-rdma&m=146545553104913&w=2 >>>>>> Hi, Leon >>>>>> Now we haven't firmware. >>>>>> But hardware still need memory for QPC\CQC\MTPT\mtt etc. >>>>> ICM stands for InfiniHost (Interconnect) Context Memory is a specific >>>>> memory place to share between host <-> FW and host <-> HW if HW is >>>>> aware of specific structures. >>>>> >>>>> I assume that in your case, it is enough to allocate memory region and >>>>> supply it to HW. Am I right? >>>> For Our hardware, >>>> 1. ICM has a memory management method, It's very good for QPC\CQC\MTPT\mtt >>>> etc. we need it. >>> You need special HW to leverage its. AFAIK it is Mellanox specific. >> For our hardware, we use ICM to memory management, the memory shared with >> host and HW. >> QPC\CQC\MTPT\mtt has specific memory requirement. >> QPC\CQC\MTPT need continuous memory. we use ICM to management the block of >> memory. It's very good！ > I wasn't convinced why do you need to copy whole ICM logic which is > specific to Mellanox. Your requirements can be implemented by standard CMA > and/or DMA. Hi, Leon In hip06 soc, Hardware need multiple memory blocks for QPC\CQC\MTPT, every block has continuous memory xxKbyte (like 128Kbyte), We need to configure the first address of 128Kbyte to hardware. For example: //------------------------------------------------------------------------ example 1: In create qp, 1. If the xx Kbyte memory that include QPC related with qpn, has not been allocated, do step 2. else do step 3. 2. dma_alloc xx Kbyte memory for QPC, and configure the first address of xx Kbyte to hardware. 3. find the QPC memory in xx Kbyte, get the dma_addr. 4. send mailbox command to hardware to create QP. In step 2, we call xx_table_get function as below to perform logic. int hns_roce_table_get(struct hns_roce_dev *hr_dev, struct hns_roce_icm_table *table, unsigned long obj) { //dma_alloc_coherent 128Kbyte memory hns_roce_alloc_icm(hr_dev, HNS_ROCE_TABLE_CHUNK_SIZE >> PAGE_SHIFT, xxxx); /*configure the first address of xx Kbyte to hardware*/ hns_roce_map_icm(hr_dev, table, obj); } In step 3, we call xx_table_find function to perform logic. void *hns_roce_table_find(struct hns_roce_icm_table *table, unsigned long obj, dma_addr_t *dma_handle); example 2: In modify qp: 1. find the QPC memory, get the virtual addr. 2. modify the fields of QPC. 3. send mailbox command to hardware to modify QP. In step 1, we call xx_table_find function to perform logic. //-------------------------------------------------------------------------- so, now we haven't a firmware, but ICM algorithm still suitable for hip06 soc perfectly. Regards Wei Hu >>>> 2. The meomry for QPC\CQC\MTPT\mtt only used for RoCE hardware and driver, >>>> we don't want use MR. >>> I didn't mean Infiniband MR, but memory region returned from standard >>> allocation functions (kmalloc, ...). >>> >>>> 3. Now we haven't firmware, maybe we need it next version. >>> You are always invited to add support once it will be needed, no need to >>> add it in advance. >>> >>> Thanks >>