From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752579AbcF2HLs (ORCPT ); Wed, 29 Jun 2016 03:11:48 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:38785 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750756AbcF2HLr (ORCPT ); Wed, 29 Jun 2016 03:11:47 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: ykk@rock-chips.com X-FST-TO: dan.carpenter@oracle.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: <832189b517212396f1528705194c8ce0> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v3 03/10] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 To: Sean Paul References: <1465904718-663-1-git-send-email-ykk@rock-chips.com> <1465904772-848-1-git-send-email-ykk@rock-chips.com> Cc: Mark Yao , Inki Dae , Jingoo Han , Heiko Stuebner , Krzysztof Kozlowski , linux-samsung-soc , linux-rockchip@lists.infradead.org, Daniel Vetter , Emil Velikov , Douglas Anderson , dri-devel , Linux Kernel Mailing List , Javier Martinez Canillas , Tomasz Figa , =?UTF-8?Q?St=c3=a9phane_Marchesin?= , Thierry Reding , Dan Carpenter From: Yakir Yang Message-ID: <577374AA.6080807@rock-chips.com> Date: Wed, 29 Jun 2016 15:11:38 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Sean, On 06/23/2016 10:33 PM, Sean Paul wrote: > On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang wrote: >> There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced >> by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special >> registers setting"). >> >> The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1 >> BIT 0, not BIT 1. >> >> Signed-off-by: Yakir Yang >> Reviewed-by: Tomasz Figa >> Tested-by: Javier Martinez Canillas > Reviewed-by: Sean Paul Thanks >> --- >> Changes in v3: >> - Add reviewed flag from Tomasz. >> [https://chromium-review.googlesource.com/#/c/346315/15] >> - Add tested flag from Javier >> >> Changes in v2: None >> >> drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h >> index 337912b..88d56ad 100644 >> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h >> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h >> @@ -163,8 +163,8 @@ >> #define HSYNC_POLARITY_CFG (0x1 << 0) >> >> /* ANALOGIX_DP_PLL_REG_1 */ >> -#define REF_CLK_24M (0x1 << 1) >> -#define REF_CLK_27M (0x0 << 1) >> +#define REF_CLK_24M (0x1 << 0) >> +#define REF_CLK_27M (0x0 << 0) >> >> /* ANALOGIX_DP_LANE_MAP */ >> #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) >> -- >> 1.9.1 >> >> >> _______________________________________________ >> dri-devel mailing list >> dri-devel@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > >