From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932385AbcHPB1K (ORCPT ); Mon, 15 Aug 2016 21:27:10 -0400 Received: from mga01.intel.com ([192.55.52.88]:4887 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932201AbcHPB1J (ORCPT ); Mon, 15 Aug 2016 21:27:09 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,527,1464678000"; d="scan'208";a="1025996723" Message-ID: <57B26BE9.3060902@intel.com> Date: Tue, 16 Aug 2016 09:27:05 +0800 From: "Yong, Jonathan" User-Agent: Mozilla/5.0 (Windows NT 6.3; Win64; x64; rv:25.4) Gecko/20150524 FossaMail/25.1.5 MIME-Version: 1.0 To: Bjorn Helgaas CC: Bjorn Helgaas , linux-pci@vger.kernel.org, intel-wired-lan@lists.osuosl.org, Jeff Kirsher , linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 0/3] PCI: Precision Time Measurement support References: <20160613185945.12503.32760.stgit@bhelgaas-glaptop2.roam.corp.google.com> <20160719211926.GB17840@localhost> <578EBC81.3090601@intel.com> <20160815185111.GC9790@localhost> In-Reply-To: <20160815185111.GC9790@localhost> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/16/2016 02:51, Bjorn Helgaas wrote: >> >> This line: >> ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT; >> >> should also set the responder capable bit (7.32.2): >> If PTM Root Capable is Set, this bit must be Set to 1b. > > The PTM Responder Capable bit (bit 1 in Table 7-145) is a HwInit bit > in the PTM Capability register, so it's read-only from the kernel's > perspective. > > The line you mention ("ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT") > is turning on bits in the PTM Control register, not the Capability > register. > My bad, there is no "responder enable" bit control, patch looks good.