From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752286AbcHQNDC (ORCPT ); Wed, 17 Aug 2016 09:03:02 -0400 Received: from foss.arm.com ([217.140.101.70]:52904 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751463AbcHQNDA (ORCPT ); Wed, 17 Aug 2016 09:03:00 -0400 Subject: Re: [PATCH v2] irqchip/gicv3: remove disabling redistributor and group1 non-secure interrupts To: Sudeep Holla , linux-kernel@vger.kernel.org References: <1471342766-18445-1-git-send-email-sudeep.holla@arm.com> <1471438159-29992-1-git-send-email-sudeep.holla@arm.com> Cc: Christopher Covington , Prashanth Prakash , Lorenzo Pieralisi , Thomas Gleixner , Jason Cooper From: Marc Zyngier Organization: ARM Ltd Message-ID: <57B46073.8090800@arm.com> Date: Wed, 17 Aug 2016 14:02:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.7.0 MIME-Version: 1.0 In-Reply-To: <1471438159-29992-1-git-send-email-sudeep.holla@arm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/08/16 13:49, Sudeep Holla wrote: > As per the GICv3 specification, to power down a processor using GICv3 > and allow automatic power-on if an interrupt must be sent to a processor, > software must set Enable to zero for all interrupt groups(by writing > to GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate. > > When commit 3708d52fc6bb ("irqchip: gic-v3: Implement CPU PM notifier") > was introduced there were no firmware implementations(in particular PSCI) > handling this. > > Linux kernel may not be aware of the CPU power state details and might > fail to identify the power states that require quiescing the CPU > interface. Even if it can be aware of those details, it can't determine > which CPU power state have been triggered at the platform level and how > the power control is implemented. > > This patch make disabling redistributor and group1 non-secure interrupts > in the power down path and re-enabling of redistributor in the power-up > path conditional. It will be handled in the kernel if and only if the > non-secure accesses are permitted to access and modify control registers. > It is left to the platform implementation otherwise. > > Cc: Marc Zyngier > Cc: Lorenzo Pieralisi > Cc: Thomas Gleixner > Cc: Jason Cooper > Tested-by: Christopher Covington > Signed-off-by: Sudeep Holla > --- > drivers/irqchip/irq-gic-v3.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > v1->v2: > - Moved gic_dist_security_disabled inside CONFIG_CPU_PM to fix > the build warning triggered otherwise. > > Hi Marc, > > Consider this as a fix for v4.8 as it fixes CPUIdle related boot hang on > Qualcomm QDF2432 platform. Applied, thanks. M. -- Jazz is not dead. It just smells funny...