From: Dongdong Liu <liudongdong3@huawei.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: <helgaas@kernel.org>, <rafael@kernel.org>,
<Lorenzo.Pieralisi@arm.com>, <tn@semihalf.com>,
<wangzhou1@hisilicon.com>, <pratyush.anand@gmail.com>,
<linux-pci@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <jcm@redhat.com>,
<gabriele.paoloni@huawei.com>, <charles.chenxin@huawei.com>,
<hanjun.guo@linaro.org>, <linuxarm@huawei.com>
Subject: Re: [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers
Date: Thu, 1 Sep 2016 10:16:02 +0800 [thread overview]
Message-ID: <57C78F62.7030803@huawei.com> (raw)
In-Reply-To: <5406169.iVLlEcSJ8X@wuerfel>
在 2016/8/31 19:48, Arnd Bergmann 写道:
> On Wednesday, August 31, 2016 7:48:14 PM CEST Dongdong Liu wrote:
>> +static struct hisi_rc_res rc_res[] = {
>> + {
>> + HIP05,
>> + {
>> + DEFINE_RES_MEM(0xb0070000, SZ_4K),
>> + DEFINE_RES_MEM(0xb0080000, SZ_4K),
>> + DEFINE_RES_MEM(0xb0090000, SZ_4K),
>> + DEFINE_RES_MEM(0xb00a0000, SZ_4K)
>> + }
>> + },
>> + {
>> + HIP06,
>> + {
>> + DEFINE_RES_MEM(0xa0090000, SZ_4K),
>> + DEFINE_RES_MEM(0xa0200000, SZ_4K),
>> + DEFINE_RES_MEM(0xa00a0000, SZ_4K),
>> + DEFINE_RES_MEM(0xa00b0000, SZ_4K)
>> + }
>> + },
>> + {
>> + HIP07,
>> + {
>> + DEFINE_RES_MEM(0xa0090000, SZ_4K),
>> + DEFINE_RES_MEM(0xa0200000, SZ_4K),
>> + DEFINE_RES_MEM(0xa00a0000, SZ_4K),
>> + DEFINE_RES_MEM(0xa00b0000, SZ_4K),
>> + DEFINE_RES_MEM(0x8a0090000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x8a0200000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x8a00a0000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x8a00b0000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x600a0090000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x600a0200000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x600a00a0000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x600a00b0000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x700a0090000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x700a0200000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x700a00a0000UL, SZ_4K),
>> + DEFINE_RES_MEM(0x700a00b0000UL, SZ_4K)
>> + }
>> + },
>
> I don't know much about ACPI, but I'm pretty sure this is not
> the normal way to find MMIO resources. Why not read them from
> the ACPI tables?
>
Hi Arnd
Our host bridge is non ECAM only for the RC bus config space;
for any other bus underneath the root bus we support ECAM access.
We have not found a comfortable ACPI way to describle RC itself config (not ECAM) resource .
Thanks
Dongdong
> Arnd
>
> .
>
next prev parent reply other threads:[~2016-09-01 2:18 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-31 11:48 [RFC PATCH V2 0/3] Add ACPI support for Hisilicon PCIe Host Controller Dongdong Liu
2016-08-31 11:48 ` [RFC PATCH V2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI Dongdong Liu
2016-08-31 11:45 ` Arnd Bergmann
2016-09-01 2:05 ` Dongdong Liu
2016-09-01 7:41 ` Arnd Bergmann
2016-09-01 12:44 ` Dongdong Liu
2016-09-01 14:02 ` Arnd Bergmann
2016-09-02 2:02 ` Dongdong Liu
2016-09-20 9:45 ` Gabriele Paoloni
2016-09-20 13:22 ` Arnd Bergmann
2016-08-31 11:48 ` [RFC PATCH V2 2/3] PCI: hisi: Add ECAM support for devices that are not RC Dongdong Liu
2016-08-31 11:48 ` [RFC PATCH V2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers Dongdong Liu
2016-08-31 11:48 ` Arnd Bergmann
2016-09-01 2:16 ` Dongdong Liu [this message]
2016-08-31 22:56 ` Rafael J. Wysocki
2016-09-01 3:23 ` Dongdong Liu
2016-09-01 23:38 ` Rafael J. Wysocki
2016-09-02 3:49 ` Dongdong Liu
-- strict thread matches above, loose matches on Subject: below --
2016-02-08 12:41 [RFC PATCH v2 0/3] Add ACPI support for HiSilicon PCIe " Gabriele Paoloni
2016-02-08 12:41 ` [RFC PATCH v2 3/3] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs " Gabriele Paoloni
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