* [PATCH v4 00/12] perf c2c: Support display for Arm64
@ 2022-05-30 11:40 Leo Yan
2022-05-30 11:40 ` [PATCH v4 01/12] perf mem: Add statistics for peer snooping Leo Yan
` (13 more replies)
0 siblings, 14 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
Arm64 Neoverse CPUs supports data source in Arm SPE trace, this allows
us to detect cache line contention and transfers.
This patch set is based on Ali Said's patch set v9 "perf: arm-spe: Decode SPE
source and use for perf c2c" [1] and Ali's patch set doesn't need any
change in this new round.
To clearly show peer loads and express the local peer loads and remote
peer lodes, this patch introduces three new metrics 'lcl_peer',
'rmt_peer' and 'tot_peer'. The display 'peer' mode uses metric
'tot_peer' for sorting cache lines.
Patches 01-05 adds statistics for memory samples, and add dimensions for
peer metrics.
Patches 06-09 are for refactoring, it refines the code with more general
naming so this can allow us to easier to extend display modes but not
strictly bound to HITM tags.
Patches 10-11 are to extend display 'peer' mode, and also changes to use
'peer' mode as default mode for Arm64 arches.
Patch 12 updates document to describe the new dimensions for peer
metrics.
This patch set has been verified for both x86 and Arm64 memory samples.
Known issues: Joe reminded there have an issue in patch set v3 that the
cache line metric shows 'N/A' for node, this is because Arm SPE trace
data doesn't contain physical address and leads to perf c2c tool fails
to find matched node range if physical address is zero. This issue is
addressed in a separte patch [2]. Since I am still using the old
perf data file (I have no Neoverse platforms), the output result still
shows the Node field is 'N/A'.
Another thing is we need to enhance data source setting for old Arm
platforms. As discussed, German would follow up this task later.
The latest patch set has been uploaded on the git server [3].
The display result with x86 memory samples:
=================================================
Shared Data Cache Line Table
=================================================
#
# ----------- Cacheline ---------- Tot ------- Load Hitm ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ----
# Index Address Node PA cnt Hitm Total LclHitm RmtHitm records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt
# ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........
#
0 0x55c8971f0080 0 1967 66.14% 252 252 0 6044 3550 2494 2024 470 0 528 2672 78 20 252 0 0 0 0
1 0x55c8971f00c0 0 1 33.86% 129 129 0 914 914 0 0 0 0 272 374 52 87 129 0 0 0 0
=================================================
Shared Cache Line Distribution Pareto
=================================================
#
# ----- HITM ----- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared
# Num RmtHitm LclHitm L1 Hit L1 Miss N/A Offset Node PA cnt Code address rmt hitm lcl hitm load records cnt Symbol Object Source:Line Node
# ..... ....... ....... ....... ....... ....... .................. .... ...... .................. ........ ........ ........ ....... ........ ...................... ................. ....................... ....
#
----------------------------------------------------------------------
0 0 252 2024 470 0 0x55c8971f0080
----------------------------------------------------------------------
0.00% 12.30% 0.00% 0.00% 0.00% 0x0 0 1 0x55c8971ed3e9 0 1313 863 1222 3 [.] 0x00000000000013e9 false_sharing.exe false_sharing.exe[13e9] 0
0.00% 0.79% 90.51% 0.00% 0.00% 0x0 0 1 0x55c8971ed3e2 0 1800 878 3029 3 [.] 0x00000000000013e2 false_sharing.exe false_sharing.exe[13e2] 0
0.00% 0.00% 9.49% 100.00% 0.00% 0x0 0 1 0x55c8971ed3f4 0 0 0 662 3 [.] 0x00000000000013f4 false_sharing.exe false_sharing.exe[13f4] 0
0.00% 86.90% 0.00% 0.00% 0.00% 0x20 0 1 0x55c8971ed447 0 141 103 1131 2 [.] 0x0000000000001447 false_sharing.exe false_sharing.exe[1447] 0
----------------------------------------------------------------------
1 0 129 0 0 0 0x55c8971f00c0
----------------------------------------------------------------------
0.00% 100.00% 0.00% 0.00% 0.00% 0x20 0 1 0x55c8971ed455 0 88 94 914 2 [.] 0x0000000000001455 false_sharing.exe false_sharing.exe[1455] 0
The display result with Arm SPE:
=================================================
Shared Data Cache Line Table
=================================================
#
# ----------- Cacheline ---------- Peer ------- Load Peer ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ----
# Index Address Node PA cnt Snoop Total Local Remote records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt
# ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........
#
0 0xaaaac17d6000 N/A 0 100.00% 99 99 0 18851 18851 0 0 0 0 0 18752 0 99 0 0 0 0 0
=================================================
Shared Cache Line Distribution Pareto
=================================================
#
# -- Peer Snoop -- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared
# Num Rmt Lcl L1 Hit L1 Miss N/A Offset Node PA cnt Code address rmt peer lcl peer load records cnt Symbol Object Source:Line Node{cpus %peers %stores}
# ..... ....... ....... ....... ....... ....... .................. .... ...... .................. ........ ........ ........ ....... ........ ...................... ................ ............... ....
#
----------------------------------------------------------------------
0 0 99 0 0 0 0xaaaac17d6000
----------------------------------------------------------------------
0.00% 6.06% 0.00% 0.00% 0.00% 0x20 N/A 0 0xaaaac17c25ac 0 375 43 18469 2 [.] 0x00000000000025ac memstress memstress[25ac] 0{ 2 100.0% n/a}
0.00% 93.94% 0.00% 0.00% 0.00% 0x29 N/A 0 0xaaaac17c3e88 0 180 173 135 2 [.] 0x0000000000003e88 memstress memstress[3e88] 0{ 2 100.0% n/a}
Changes from v3:
* Changed to display remote and local peer accesses (Joe);
* Fixed the usage info for display types (Joe);
* Do not display HITM dimensions when use 'peer' display, and HITM
display doesn't show any 'peer' dimensions (James);
* Split to smaller patches for adding dimensions of peer operations;
* Updated documentation to reflect the latest GUI and stdio.
Changes from v2:
* Updated patch 04 to account metrics for both cache level and ld_peer
for PEER flag;
* Updated document for metric 'rmt_hit' which is accounted for all
remote accesses (include remote DRAM and any upward caches).
Changes from v1:
* Updated patches 01, 02 and 03 to support 'N/A' metrics for store
operations, so can align with the patch set [1] for store samples.
[1] https://lore.kernel.org/lkml/20220517020326.18580-1-alisaidi@amazon.com/
[2] https://lore.kernel.org/lkml/20220530083645.253432-1-leo.yan@linaro.org/
[3] https://git.linaro.org/people/leo.yan/linux-spe.git/ branch: perf_c2c_arm_spe_peer_v4
Leo Yan (12):
perf mem: Add statistics for peer snooping
perf c2c: Output statistics for peer snooping
perf c2c: Add dimensions for peer load operations
perf c2c: Add dimensions of peer metrics for cache line view
perf c2c: Add mean dimensions for peer operations
perf c2c: Use explicit names for display macros
perf c2c: Rename dimension from 'percent_hitm' to
'percent_costly_snoop'
perf c2c: Refactor node header
perf c2c: Refactor display string
perf c2c: Sort on peer snooping for load operations
perf c2c: Use 'peer' as default display for Arm64
perf c2c: Update documentation for new display option 'peer'
tools/perf/Documentation/perf-c2c.txt | 30 +-
tools/perf/builtin-c2c.c | 454 ++++++++++++++++++++------
tools/perf/util/mem-events.c | 28 +-
tools/perf/util/mem-events.h | 3 +
4 files changed, 403 insertions(+), 112 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 01/12] perf mem: Add statistics for peer snooping
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 02/12] perf c2c: Output " Leo Yan
` (12 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
Since the flag PERF_MEM_SNOOPX_PEER is added to support cache snooping
from peer cache line, it can come from a peer core, a peer cluster, or
a remote NUMA node.
This patch adds statistics for the flag PERF_MEM_SNOOPX_PEER. Note, we
take PERF_MEM_SNOOPX_PEER as an affiliated info, it needs to cooperate
with cache level statistics. Therefore, we account the load operations
for both the cache level's metrics (e.g. ld_l2hit, ld_llchit, etc.) and
peer related metrics when flag PERF_MEM_SNOOPX_PEER is set.
So three new metrics are introduced: 'lcl_peer' is for local cache
access, the metric 'rmt_peer' is for remote access (includes remote DRAM
and any caches in remote node), and the metric 'tot_peer' is accounting
the sum value of 'lcl_peer' and 'rmt_peer'.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/util/mem-events.c | 28 +++++++++++++++++++++++++---
tools/perf/util/mem-events.h | 3 +++
2 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c
index 5dca1882c284..764883183519 100644
--- a/tools/perf/util/mem-events.c
+++ b/tools/perf/util/mem-events.c
@@ -525,6 +525,7 @@ int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi)
u64 op = data_src->mem_op;
u64 lvl = data_src->mem_lvl;
u64 snoop = data_src->mem_snoop;
+ u64 snoopx = data_src->mem_snoopx;
u64 lock = data_src->mem_lock;
u64 blk = data_src->mem_blk;
/*
@@ -544,6 +545,12 @@ do { \
stats->tot_hitm++; \
} while (0)
+#define PEER_INC(__f) \
+do { \
+ stats->__f++; \
+ stats->tot_peer++; \
+} while (0)
+
#define P(a, b) PERF_MEM_##a##_##b
stats->nr_entries++;
@@ -567,12 +574,20 @@ do { \
if (lvl & P(LVL, IO)) stats->ld_io++;
if (lvl & P(LVL, LFB)) stats->ld_fbhit++;
if (lvl & P(LVL, L1 )) stats->ld_l1hit++;
- if (lvl & P(LVL, L2 )) stats->ld_l2hit++;
+ if (lvl & P(LVL, L2)) {
+ stats->ld_l2hit++;
+
+ if (snoopx & P(SNOOPX, PEER))
+ PEER_INC(lcl_peer);
+ }
if (lvl & P(LVL, L3 )) {
if (snoop & P(SNOOP, HITM))
HITM_INC(lcl_hitm);
else
stats->ld_llchit++;
+
+ if (snoopx & P(SNOOPX, PEER))
+ PEER_INC(lcl_peer);
}
if (lvl & P(LVL, LOC_RAM)) {
@@ -597,10 +612,14 @@ do { \
if ((lvl & P(LVL, REM_CCE1)) ||
(lvl & P(LVL, REM_CCE2)) ||
mrem) {
- if (snoop & P(SNOOP, HIT))
+ if (snoop & P(SNOOP, HIT)) {
stats->rmt_hit++;
- else if (snoop & P(SNOOP, HITM))
+ } else if (snoop & P(SNOOP, HITM)) {
HITM_INC(rmt_hitm);
+ } else if (snoopx & P(SNOOPX, PEER)) {
+ stats->rmt_hit++;
+ PEER_INC(rmt_peer);
+ }
}
if ((lvl & P(LVL, MISS)))
@@ -664,6 +683,9 @@ void c2c_add_stats(struct c2c_stats *stats, struct c2c_stats *add)
stats->lcl_hitm += add->lcl_hitm;
stats->rmt_hitm += add->rmt_hitm;
stats->tot_hitm += add->tot_hitm;
+ stats->lcl_peer += add->lcl_peer;
+ stats->rmt_peer += add->rmt_peer;
+ stats->tot_peer += add->tot_peer;
stats->rmt_hit += add->rmt_hit;
stats->lcl_dram += add->lcl_dram;
stats->rmt_dram += add->rmt_dram;
diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h
index 8a8b568baeee..12372309d60e 100644
--- a/tools/perf/util/mem-events.h
+++ b/tools/perf/util/mem-events.h
@@ -78,6 +78,9 @@ struct c2c_stats {
u32 lcl_hitm; /* count of loads with local HITM */
u32 rmt_hitm; /* count of loads with remote HITM */
u32 tot_hitm; /* count of loads with local and remote HITM */
+ u32 lcl_peer; /* count of loads with local peer cache */
+ u32 rmt_peer; /* count of loads with remote peer cache */
+ u32 tot_peer; /* count of loads with local and remote peer cache */
u32 rmt_hit; /* count of loads with remote hit clean; */
u32 lcl_dram; /* count of loads miss to local DRAM */
u32 rmt_dram; /* count of loads miss to remote DRAM */
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 02/12] perf c2c: Output statistics for peer snooping
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
2022-05-30 11:40 ` [PATCH v4 01/12] perf mem: Add statistics for peer snooping Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 03/12] perf c2c: Add dimensions for peer load operations Leo Yan
` (11 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
This patch outputs statistics for peer snooping for whole trace events
and global shared cache line.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/builtin-c2c.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index e8280973d7b8..ac389432c15f 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -2202,6 +2202,8 @@ static void print_c2c__display_stats(FILE *out)
fprintf(out, " Load LLC Misses : %10d\n", llc_misses);
fprintf(out, " Load access blocked by data : %10d\n", stats->blk_data);
fprintf(out, " Load access blocked by address : %10d\n", stats->blk_addr);
+ fprintf(out, " Load HIT Local Peer : %10d\n", stats->lcl_peer);
+ fprintf(out, " Load HIT Remote Peer : %10d\n", stats->rmt_peer);
fprintf(out, " LLC Misses to Local DRAM : %10.1f%%\n", ((double)stats->lcl_dram/(double)llc_misses) * 100.);
fprintf(out, " LLC Misses to Remote DRAM : %10.1f%%\n", ((double)stats->rmt_dram/(double)llc_misses) * 100.);
fprintf(out, " LLC Misses to Remote cache (HIT) : %10.1f%%\n", ((double)stats->rmt_hit /(double)llc_misses) * 100.);
@@ -2230,6 +2232,7 @@ static void print_shared_cacheline_info(FILE *out)
fprintf(out, " L1D hits on shared lines : %10d\n", stats->ld_l1hit);
fprintf(out, " L2D hits on shared lines : %10d\n", stats->ld_l2hit);
fprintf(out, " LLC hits on shared lines : %10d\n", stats->ld_llchit + stats->lcl_hitm);
+ fprintf(out, " Load hits on peer cache or nodes : %10d\n", stats->lcl_peer + stats->rmt_peer);
fprintf(out, " Locked Access on shared lines : %10d\n", stats->locks);
fprintf(out, " Blocked Access on shared lines : %10d\n", stats->blk_data + stats->blk_addr);
fprintf(out, " Store HITs on shared lines : %10d\n", stats->store);
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 03/12] perf c2c: Add dimensions for peer load operations
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
2022-05-30 11:40 ` [PATCH v4 01/12] perf mem: Add statistics for peer snooping Leo Yan
2022-05-30 11:40 ` [PATCH v4 02/12] perf c2c: Output " Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 04/12] perf c2c: Add dimensions of peer metrics for cache line view Leo Yan
` (10 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
This patch adds three dimensions for peer load operations of 'lcl_peer',
'rmt_peer' and 'tot_peer'. These three dimensions will be used in the
shared data cache line table.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/builtin-c2c.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index ac389432c15f..2d7991d372a6 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -650,6 +650,9 @@ __f ## _cmp(struct perf_hpp_fmt *fmt __maybe_unused, \
STAT_FN(rmt_hitm)
STAT_FN(lcl_hitm)
+STAT_FN(rmt_peer)
+STAT_FN(lcl_peer)
+STAT_FN(tot_peer)
STAT_FN(store)
STAT_FN(st_l1hit)
STAT_FN(st_l1miss)
@@ -1360,6 +1363,30 @@ static struct c2c_dimension dim_rmt_hitm = {
.width = 7,
};
+static struct c2c_dimension dim_tot_peer = {
+ .header = HEADER_SPAN("------- Load Peer -------", "Total", 2),
+ .name = "tot_peer",
+ .cmp = tot_peer_cmp,
+ .entry = tot_peer_entry,
+ .width = 7,
+};
+
+static struct c2c_dimension dim_lcl_peer = {
+ .header = HEADER_SPAN_LOW("Local"),
+ .name = "lcl_peer",
+ .cmp = lcl_peer_cmp,
+ .entry = lcl_peer_entry,
+ .width = 7,
+};
+
+static struct c2c_dimension dim_rmt_peer = {
+ .header = HEADER_SPAN_LOW("Remote"),
+ .name = "rmt_peer",
+ .cmp = rmt_peer_cmp,
+ .entry = rmt_peer_entry,
+ .width = 7,
+};
+
static struct c2c_dimension dim_cl_rmt_hitm = {
.header = HEADER_SPAN("----- HITM -----", "Rmt", 1),
.name = "cl_rmt_hitm",
@@ -1672,6 +1699,9 @@ static struct c2c_dimension *dimensions[] = {
&dim_tot_hitm,
&dim_lcl_hitm,
&dim_rmt_hitm,
+ &dim_tot_peer,
+ &dim_lcl_peer,
+ &dim_rmt_peer,
&dim_cl_lcl_hitm,
&dim_cl_rmt_hitm,
&dim_tot_stores,
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 04/12] perf c2c: Add dimensions of peer metrics for cache line view
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (2 preceding siblings ...)
2022-05-30 11:40 ` [PATCH v4 03/12] perf c2c: Add dimensions for peer load operations Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 05/12] perf c2c: Add mean dimensions for peer operations Leo Yan
` (9 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
This patch adds dimensions of peer ops, which will be used for Shared
cache line distribution pareto.
It adds the percentage dimensions for local and remote peer operations,
and the dimensions for accounting operation numbers which is used for
stdio mode.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/builtin-c2c.c | 102 +++++++++++++++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index 2d7991d372a6..85768c526f9d 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -902,6 +902,8 @@ static double percent_ ## __f(struct c2c_hist_entry *c2c_he) \
PERCENT_FN(rmt_hitm)
PERCENT_FN(lcl_hitm)
+PERCENT_FN(rmt_peer)
+PERCENT_FN(lcl_peer)
PERCENT_FN(st_l1hit)
PERCENT_FN(st_l1miss)
PERCENT_FN(st_na)
@@ -968,6 +970,68 @@ percent_lcl_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused,
return per_left - per_right;
}
+static int
+percent_lcl_peer_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
+ struct hist_entry *he)
+{
+ int width = c2c_width(fmt, hpp, he->hists);
+ double per = PERCENT(he, lcl_peer);
+ char buf[10];
+
+ return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per));
+}
+
+static int
+percent_lcl_peer_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
+ struct hist_entry *he)
+{
+ return percent_color(fmt, hpp, he, percent_lcl_peer);
+}
+
+static int64_t
+percent_lcl_peer_cmp(struct perf_hpp_fmt *fmt __maybe_unused,
+ struct hist_entry *left, struct hist_entry *right)
+{
+ double per_left;
+ double per_right;
+
+ per_left = PERCENT(left, lcl_peer);
+ per_right = PERCENT(right, lcl_peer);
+
+ return per_left - per_right;
+}
+
+static int
+percent_rmt_peer_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
+ struct hist_entry *he)
+{
+ int width = c2c_width(fmt, hpp, he->hists);
+ double per = PERCENT(he, rmt_peer);
+ char buf[10];
+
+ return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per));
+}
+
+static int
+percent_rmt_peer_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
+ struct hist_entry *he)
+{
+ return percent_color(fmt, hpp, he, percent_rmt_peer);
+}
+
+static int64_t
+percent_rmt_peer_cmp(struct perf_hpp_fmt *fmt __maybe_unused,
+ struct hist_entry *left, struct hist_entry *right)
+{
+ double per_left;
+ double per_right;
+
+ per_left = PERCENT(left, rmt_peer);
+ per_right = PERCENT(right, rmt_peer);
+
+ return per_left - per_right;
+}
+
static int
percent_stores_l1hit_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
struct hist_entry *he)
@@ -1403,6 +1467,22 @@ static struct c2c_dimension dim_cl_lcl_hitm = {
.width = 7,
};
+static struct c2c_dimension dim_cl_rmt_peer = {
+ .header = HEADER_SPAN("----- Peer -----", "Rmt", 1),
+ .name = "cl_rmt_peer",
+ .cmp = rmt_peer_cmp,
+ .entry = rmt_peer_entry,
+ .width = 7,
+};
+
+static struct c2c_dimension dim_cl_lcl_peer = {
+ .header = HEADER_SPAN_LOW("Lcl"),
+ .name = "cl_lcl_peer",
+ .cmp = lcl_peer_cmp,
+ .entry = lcl_peer_entry,
+ .width = 7,
+};
+
static struct c2c_dimension dim_tot_stores = {
.header = HEADER_BOTH("Total", "Stores"),
.name = "tot_stores",
@@ -1547,6 +1627,24 @@ static struct c2c_dimension dim_percent_lcl_hitm = {
.width = 7,
};
+static struct c2c_dimension dim_percent_rmt_peer = {
+ .header = HEADER_SPAN("-- Peer Snoop --", "Rmt", 1),
+ .name = "percent_rmt_peer",
+ .cmp = percent_rmt_peer_cmp,
+ .entry = percent_rmt_peer_entry,
+ .color = percent_rmt_peer_color,
+ .width = 7,
+};
+
+static struct c2c_dimension dim_percent_lcl_peer = {
+ .header = HEADER_SPAN_LOW("Lcl"),
+ .name = "percent_lcl_peer",
+ .cmp = percent_lcl_peer_cmp,
+ .entry = percent_lcl_peer_entry,
+ .color = percent_lcl_peer_color,
+ .width = 7,
+};
+
static struct c2c_dimension dim_percent_stores_l1hit = {
.header = HEADER_SPAN("------- Store Refs ------", "L1 Hit", 2),
.name = "percent_stores_l1hit",
@@ -1704,6 +1802,8 @@ static struct c2c_dimension *dimensions[] = {
&dim_rmt_peer,
&dim_cl_lcl_hitm,
&dim_cl_rmt_hitm,
+ &dim_cl_lcl_peer,
+ &dim_cl_rmt_peer,
&dim_tot_stores,
&dim_stores_l1hit,
&dim_stores_l1miss,
@@ -1721,6 +1821,8 @@ static struct c2c_dimension *dimensions[] = {
&dim_percent_hitm,
&dim_percent_rmt_hitm,
&dim_percent_lcl_hitm,
+ &dim_percent_rmt_peer,
+ &dim_percent_lcl_peer,
&dim_percent_stores_l1hit,
&dim_percent_stores_l1miss,
&dim_percent_stores_na,
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 05/12] perf c2c: Add mean dimensions for peer operations
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (3 preceding siblings ...)
2022-05-30 11:40 ` [PATCH v4 04/12] perf c2c: Add dimensions of peer metrics for cache line view Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 06/12] perf c2c: Use explicit names for display macros Leo Yan
` (8 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
This patch adds two dimensions for the mean value of peer operations.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/builtin-c2c.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index 85768c526f9d..01a0656537f6 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -55,6 +55,8 @@ struct c2c_hists {
struct compute_stats {
struct stats lcl_hitm;
struct stats rmt_hitm;
+ struct stats lcl_peer;
+ struct stats rmt_peer;
struct stats load;
};
@@ -154,6 +156,8 @@ static void *c2c_he_zalloc(size_t size)
init_stats(&c2c_he->cstats.lcl_hitm);
init_stats(&c2c_he->cstats.rmt_hitm);
+ init_stats(&c2c_he->cstats.lcl_peer);
+ init_stats(&c2c_he->cstats.rmt_peer);
init_stats(&c2c_he->cstats.load);
return &c2c_he->he;
@@ -253,6 +257,10 @@ static void compute_stats(struct c2c_hist_entry *c2c_he,
update_stats(&cstats->rmt_hitm, weight);
else if (stats->lcl_hitm)
update_stats(&cstats->lcl_hitm, weight);
+ else if (stats->rmt_peer)
+ update_stats(&cstats->rmt_peer, weight);
+ else if (stats->lcl_peer)
+ update_stats(&cstats->lcl_peer, weight);
else if (stats->load)
update_stats(&cstats->load, weight);
}
@@ -1280,6 +1288,8 @@ __func(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, struct hist_entry *he) \
MEAN_ENTRY(mean_rmt_entry, rmt_hitm);
MEAN_ENTRY(mean_lcl_entry, lcl_hitm);
MEAN_ENTRY(mean_load_entry, load);
+MEAN_ENTRY(mean_rmt_peer_entry, rmt_peer);
+MEAN_ENTRY(mean_lcl_peer_entry, lcl_peer);
static int
cpucnt_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
@@ -1750,6 +1760,22 @@ static struct c2c_dimension dim_mean_load = {
.width = 8,
};
+static struct c2c_dimension dim_mean_rmt_peer = {
+ .header = HEADER_SPAN("---------- cycles ----------", "rmt peer", 2),
+ .name = "mean_rmt_peer",
+ .cmp = empty_cmp,
+ .entry = mean_rmt_peer_entry,
+ .width = 8,
+};
+
+static struct c2c_dimension dim_mean_lcl_peer = {
+ .header = HEADER_SPAN_LOW("lcl peer"),
+ .name = "mean_lcl_peer",
+ .cmp = empty_cmp,
+ .entry = mean_lcl_peer_entry,
+ .width = 8,
+};
+
static struct c2c_dimension dim_cpucnt = {
.header = HEADER_BOTH("cpu", "cnt"),
.name = "cpucnt",
@@ -1835,6 +1861,8 @@ static struct c2c_dimension *dimensions[] = {
&dim_node,
&dim_mean_rmt,
&dim_mean_lcl,
+ &dim_mean_rmt_peer,
+ &dim_mean_lcl_peer,
&dim_mean_load,
&dim_cpucnt,
&dim_srcline,
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 06/12] perf c2c: Use explicit names for display macros
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (4 preceding siblings ...)
2022-05-30 11:40 ` [PATCH v4 05/12] perf c2c: Add mean dimensions for peer operations Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 07/12] perf c2c: Rename dimension from 'percent_hitm' to 'percent_costly_snoop' Leo Yan
` (7 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
Perf c2c tool has an assumption that it heavily depends on HITM snoop
type to detect cache false sharing, unfortunately, HITM is not supported
on some architectures.
Essentially, perf c2c tool wants to find some very costly snooping
operations for false cache sharing, this means it's not necessarily
to stick using HITM tags and we can explore other snooping types
(e.g. SNOOPX_PEER).
For this reason, this patch renames HITM related display macros with
suffix '_HITM', so it can be distinct if later add more display types
for on other snooping type.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Ali Saidi <alisaidi@amazon.com>
---
tools/perf/builtin-c2c.c | 58 ++++++++++++++++++++--------------------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index 01a0656537f6..b50b23ea28ec 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -115,16 +115,16 @@ struct perf_c2c {
};
enum {
- DISPLAY_LCL,
- DISPLAY_RMT,
- DISPLAY_TOT,
+ DISPLAY_LCL_HITM,
+ DISPLAY_RMT_HITM,
+ DISPLAY_TOT_HITM,
DISPLAY_MAX,
};
static const char *display_str[DISPLAY_MAX] = {
- [DISPLAY_LCL] = "Local",
- [DISPLAY_RMT] = "Remote",
- [DISPLAY_TOT] = "Total",
+ [DISPLAY_LCL_HITM] = "Local",
+ [DISPLAY_RMT_HITM] = "Remote",
+ [DISPLAY_TOT_HITM] = "Total",
};
static const struct option c2c_options[] = {
@@ -811,15 +811,15 @@ static double percent_hitm(struct c2c_hist_entry *c2c_he)
total = &hists->stats;
switch (c2c.display) {
- case DISPLAY_RMT:
+ case DISPLAY_RMT_HITM:
st = stats->rmt_hitm;
tot = total->rmt_hitm;
break;
- case DISPLAY_LCL:
+ case DISPLAY_LCL_HITM:
st = stats->lcl_hitm;
tot = total->lcl_hitm;
break;
- case DISPLAY_TOT:
+ case DISPLAY_TOT_HITM:
st = stats->tot_hitm;
tot = total->tot_hitm;
default:
@@ -1217,15 +1217,15 @@ node_entry(struct perf_hpp_fmt *fmt __maybe_unused, struct perf_hpp *hpp,
advance_hpp(hpp, ret);
switch (c2c.display) {
- case DISPLAY_RMT:
+ case DISPLAY_RMT_HITM:
ret = display_metrics(hpp, stats->rmt_hitm,
c2c_he->stats.rmt_hitm);
break;
- case DISPLAY_LCL:
+ case DISPLAY_LCL_HITM:
ret = display_metrics(hpp, stats->lcl_hitm,
c2c_he->stats.lcl_hitm);
break;
- case DISPLAY_TOT:
+ case DISPLAY_TOT_HITM:
ret = display_metrics(hpp, stats->tot_hitm,
c2c_he->stats.tot_hitm);
break;
@@ -1606,9 +1606,9 @@ static struct c2c_dimension dim_tot_loads = {
};
static struct c2c_header percent_hitm_header[] = {
- [DISPLAY_LCL] = HEADER_BOTH("Lcl", "Hitm"),
- [DISPLAY_RMT] = HEADER_BOTH("Rmt", "Hitm"),
- [DISPLAY_TOT] = HEADER_BOTH("Tot", "Hitm"),
+ [DISPLAY_LCL_HITM] = HEADER_BOTH("Lcl", "Hitm"),
+ [DISPLAY_RMT_HITM] = HEADER_BOTH("Rmt", "Hitm"),
+ [DISPLAY_TOT_HITM] = HEADER_BOTH("Tot", "Hitm"),
};
static struct c2c_dimension dim_percent_hitm = {
@@ -2101,15 +2101,15 @@ static bool he__display(struct hist_entry *he, struct c2c_stats *stats)
c2c_he = container_of(he, struct c2c_hist_entry, he);
switch (c2c.display) {
- case DISPLAY_LCL:
+ case DISPLAY_LCL_HITM:
he->filtered = filter_display(c2c_he->stats.lcl_hitm,
stats->lcl_hitm);
break;
- case DISPLAY_RMT:
+ case DISPLAY_RMT_HITM:
he->filtered = filter_display(c2c_he->stats.rmt_hitm,
stats->rmt_hitm);
break;
- case DISPLAY_TOT:
+ case DISPLAY_TOT_HITM:
he->filtered = filter_display(c2c_he->stats.tot_hitm,
stats->tot_hitm);
break;
@@ -2132,13 +2132,13 @@ static inline bool is_valid_hist_entry(struct hist_entry *he)
return true;
switch (c2c.display) {
- case DISPLAY_LCL:
+ case DISPLAY_LCL_HITM:
has_record = !!c2c_he->stats.lcl_hitm;
break;
- case DISPLAY_RMT:
+ case DISPLAY_RMT_HITM:
has_record = !!c2c_he->stats.rmt_hitm;
break;
- case DISPLAY_TOT:
+ case DISPLAY_TOT_HITM:
has_record = !!c2c_he->stats.tot_hitm;
break;
default:
@@ -2835,11 +2835,11 @@ static int setup_display(const char *str)
const char *display = str ?: "tot";
if (!strcmp(display, "tot"))
- c2c.display = DISPLAY_TOT;
+ c2c.display = DISPLAY_TOT_HITM;
else if (!strcmp(display, "rmt"))
- c2c.display = DISPLAY_RMT;
+ c2c.display = DISPLAY_RMT_HITM;
else if (!strcmp(display, "lcl"))
- c2c.display = DISPLAY_LCL;
+ c2c.display = DISPLAY_LCL_HITM;
else {
pr_err("failed: unknown display type: %s\n", str);
return -1;
@@ -2927,9 +2927,9 @@ static int setup_coalesce(const char *coalesce, bool no_source)
return -1;
if (asprintf(&c2c.cl_resort, "offset,%s",
- c2c.display == DISPLAY_TOT ?
+ c2c.display == DISPLAY_TOT_HITM ?
"tot_hitm" :
- c2c.display == DISPLAY_RMT ?
+ c2c.display == DISPLAY_RMT_HITM ?
"rmt_hitm,lcl_hitm" :
"lcl_hitm,rmt_hitm") < 0)
return -ENOMEM;
@@ -3085,11 +3085,11 @@ static int perf_c2c__report(int argc, const char **argv)
"ld_rmthit,rmt_hitm,"
"dram_lcl,dram_rmt";
- if (c2c.display == DISPLAY_TOT)
+ if (c2c.display == DISPLAY_TOT_HITM)
sort_str = "tot_hitm";
- else if (c2c.display == DISPLAY_RMT)
+ else if (c2c.display == DISPLAY_RMT_HITM)
sort_str = "rmt_hitm";
- else if (c2c.display == DISPLAY_LCL)
+ else if (c2c.display == DISPLAY_LCL_HITM)
sort_str = "lcl_hitm";
c2c_hists__reinit(&c2c.hists, output_str, sort_str);
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 07/12] perf c2c: Rename dimension from 'percent_hitm' to 'percent_costly_snoop'
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (5 preceding siblings ...)
2022-05-30 11:40 ` [PATCH v4 06/12] perf c2c: Use explicit names for display macros Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 08/12] perf c2c: Refactor node header Leo Yan
` (6 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
Use more general naming for the main sort dimension, this can allow us
not to sort only on HITM snoop type, so it can be extended to support
other costly snooping operations. So rename the dimension to the prefix
'percent_costly_".
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Ali Saidi <alisaidi@amazon.com>
---
tools/perf/builtin-c2c.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index b50b23ea28ec..d3608d24bea4 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -798,7 +798,7 @@ percent_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
return hpp_color_scnprintf(hpp, "%*.2f%%", width - 1, per);
}
-static double percent_hitm(struct c2c_hist_entry *c2c_he)
+static double percent_costly_snoop(struct c2c_hist_entry *c2c_he)
{
struct c2c_hists *hists;
struct c2c_stats *stats;
@@ -838,8 +838,8 @@ static double percent_hitm(struct c2c_hist_entry *c2c_he)
})
static int
-percent_hitm_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
- struct hist_entry *he)
+percent_costly_snoop_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
+ struct hist_entry *he)
{
struct c2c_hist_entry *c2c_he;
int width = c2c_width(fmt, hpp, he->hists);
@@ -847,20 +847,20 @@ percent_hitm_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
double per;
c2c_he = container_of(he, struct c2c_hist_entry, he);
- per = percent_hitm(c2c_he);
+ per = percent_costly_snoop(c2c_he);
return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per));
}
static int
-percent_hitm_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
- struct hist_entry *he)
+percent_costly_snoop_color(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
+ struct hist_entry *he)
{
- return percent_color(fmt, hpp, he, percent_hitm);
+ return percent_color(fmt, hpp, he, percent_costly_snoop);
}
static int64_t
-percent_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused,
- struct hist_entry *left, struct hist_entry *right)
+percent_costly_snoop_cmp(struct perf_hpp_fmt *fmt __maybe_unused,
+ struct hist_entry *left, struct hist_entry *right)
{
struct c2c_hist_entry *c2c_left;
struct c2c_hist_entry *c2c_right;
@@ -870,8 +870,8 @@ percent_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused,
c2c_left = container_of(left, struct c2c_hist_entry, he);
c2c_right = container_of(right, struct c2c_hist_entry, he);
- per_left = percent_hitm(c2c_left);
- per_right = percent_hitm(c2c_right);
+ per_left = percent_costly_snoop(c2c_left);
+ per_right = percent_costly_snoop(c2c_right);
return per_left - per_right;
}
@@ -1605,17 +1605,17 @@ static struct c2c_dimension dim_tot_loads = {
.width = 7,
};
-static struct c2c_header percent_hitm_header[] = {
+static struct c2c_header percent_costly_snoop_header[] = {
[DISPLAY_LCL_HITM] = HEADER_BOTH("Lcl", "Hitm"),
[DISPLAY_RMT_HITM] = HEADER_BOTH("Rmt", "Hitm"),
[DISPLAY_TOT_HITM] = HEADER_BOTH("Tot", "Hitm"),
};
-static struct c2c_dimension dim_percent_hitm = {
- .name = "percent_hitm",
- .cmp = percent_hitm_cmp,
- .entry = percent_hitm_entry,
- .color = percent_hitm_color,
+static struct c2c_dimension dim_percent_costly_snoop = {
+ .name = "percent_costly_snoop",
+ .cmp = percent_costly_snoop_cmp,
+ .entry = percent_costly_snoop_entry,
+ .color = percent_costly_snoop_color,
.width = 7,
};
@@ -1844,7 +1844,7 @@ static struct c2c_dimension *dimensions[] = {
&dim_ld_rmthit,
&dim_tot_recs,
&dim_tot_loads,
- &dim_percent_hitm,
+ &dim_percent_costly_snoop,
&dim_percent_rmt_hitm,
&dim_percent_lcl_hitm,
&dim_percent_rmt_peer,
@@ -2748,7 +2748,7 @@ static int ui_quirks(void)
nodestr = "CL";
}
- dim_percent_hitm.header = percent_hitm_header[c2c.display];
+ dim_percent_costly_snoop.header = percent_costly_snoop_header[c2c.display];
/* Fix the zero line for dcacheline column. */
buf = fill_line("Cacheline", dim_dcacheline.width +
@@ -3074,7 +3074,7 @@ static int perf_c2c__report(int argc, const char **argv)
"dcacheline,"
"dcacheline_node,"
"dcacheline_count,"
- "percent_hitm,"
+ "percent_costly_snoop,"
"tot_hitm,lcl_hitm,rmt_hitm,"
"tot_recs,"
"tot_loads,"
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 08/12] perf c2c: Refactor node header
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (6 preceding siblings ...)
2022-05-30 11:40 ` [PATCH v4 07/12] perf c2c: Rename dimension from 'percent_hitm' to 'percent_costly_snoop' Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 09/12] perf c2c: Refactor display string Leo Yan
` (5 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
The node header array contains 3 items, each item is used for one of
the 3 flavors for node accessing info. To extend sorting on other
snooping type and not always stick to HITMs, the second header string
"Node{cpus %hitms %stores}" should be adjusted (e.g. it's changed as
"Node{cpus %peer %stores}").
For this reason, this patch changes the node header array to three
flat variables and uses switch-case in function setup_nodes_header(),
thus it is easier for altering the header string.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Ali Saidi <alisaidi@amazon.com>
---
tools/perf/builtin-c2c.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index d3608d24bea4..e76219034588 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -1723,12 +1723,6 @@ static struct c2c_dimension dim_dso = {
.se = &sort_dso,
};
-static struct c2c_header header_node[3] = {
- HEADER_LOW("Node"),
- HEADER_LOW("Node{cpus %hitms %stores}"),
- HEADER_LOW("Node{cpu list}"),
-};
-
static struct c2c_dimension dim_node = {
.name = "node",
.cmp = empty_cmp,
@@ -2229,9 +2223,27 @@ static int resort_cl_cb(struct hist_entry *he, void *arg __maybe_unused)
return 0;
}
+static struct c2c_header header_node_0 = HEADER_LOW("Node");
+static struct c2c_header header_node_1 = HEADER_LOW("Node{cpus %hitms %stores}");
+static struct c2c_header header_node_2 = HEADER_LOW("Node{cpu list}");
+
static void setup_nodes_header(void)
{
- dim_node.header = header_node[c2c.node_info];
+ switch (c2c.node_info) {
+ case 0:
+ dim_node.header = header_node_0;
+ break;
+ case 1:
+ dim_node.header = header_node_1;
+ break;
+ case 2:
+ dim_node.header = header_node_2;
+ break;
+ default:
+ break;
+ }
+
+ return;
}
static int setup_nodes(struct perf_session *session)
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 09/12] perf c2c: Refactor display string
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (7 preceding siblings ...)
2022-05-30 11:40 ` [PATCH v4 08/12] perf c2c: Refactor node header Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 10/12] perf c2c: Sort on peer snooping for load operations Leo Yan
` (4 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
The display type is shown by combination the display string array and a
suffix string "HITMs", which is not friendly to extend display for other
sorting type (e.g. extension for peer operations).
This patch moves the suffix string "HITMs" into display string array for
HITM types, so it can allow us to not necessarily to output string
"HITMs" for new incoming display type.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/builtin-c2c.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index e76219034588..725b23d9104b 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -122,9 +122,9 @@ enum {
};
static const char *display_str[DISPLAY_MAX] = {
- [DISPLAY_LCL_HITM] = "Local",
- [DISPLAY_RMT_HITM] = "Remote",
- [DISPLAY_TOT_HITM] = "Total",
+ [DISPLAY_LCL_HITM] = "Local HITMs",
+ [DISPLAY_RMT_HITM] = "Remote HITMs",
+ [DISPLAY_TOT_HITM] = "Total HITMs",
};
static const struct option c2c_options[] = {
@@ -2489,7 +2489,7 @@ static void print_c2c_info(FILE *out, struct perf_session *session)
fprintf(out, "%-36s: %s\n", first ? " Events" : "", evsel__name(evsel));
first = false;
}
- fprintf(out, " Cachelines sort on : %s HITMs\n",
+ fprintf(out, " Cachelines sort on : %s\n",
display_str[c2c.display]);
fprintf(out, " Cacheline data grouping : %s\n", c2c.cl_sort);
}
@@ -2646,7 +2646,7 @@ static int perf_c2c_browser__title(struct hist_browser *browser,
{
scnprintf(bf, size,
"Shared Data Cache Line Table "
- "(%lu entries, sorted on %s HITMs)",
+ "(%lu entries, sorted on %s)",
browser->nr_non_filtered_entries,
display_str[c2c.display]);
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 10/12] perf c2c: Sort on peer snooping for load operations
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (8 preceding siblings ...)
2022-05-30 11:40 ` [PATCH v4 09/12] perf c2c: Refactor display string Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 11/12] perf c2c: Use 'peer' as default display for Arm64 Leo Yan
` (3 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
This patch adds a new option 'peer' so can sort on the cache hit for
peer snooping.
For displaying with option 'peer', the "Shared Data Cache Line Table"
and "Shared Cache Line Distribution Pareto" both sort with the metrics
"tot_peer".
As result, we can get the 'peer' display:
# perf c2c report -d peer --coalesce tid,pid,iaddr,dso -N --stdio
=================================================
Shared Data Cache Line Table
=================================================
#
# ----------- Cacheline ---------- Peer ------- Load Peer ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ----
# Index Address Node PA cnt Snoop Total Local Remote records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt
# ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........
#
0 0xaaaac17d6000 N/A 0 100.00% 99 99 0 18851 18851 0 0 0 0 0 18752 0 99 0 0 0 0 0
=================================================
Shared Cache Line Distribution Pareto
=================================================
#
# -- Peer Snoop -- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared
# Num Rmt Lcl L1 Hit L1 Miss N/A Offset Node PA cnt Pid Tid Code address rmt peer lcl peer load records cnt Symbol Object Source:Line Node{cpus %peers %stores}
# ..... ....... ....... ....... ....... ....... .................. .... ...... ....... ................. .................. ........ ........ ........ ....... ........ ...................... ................ ............... ....
#
----------------------------------------------------------------------
0 0 99 0 0 0 0xaaaac17d6000
----------------------------------------------------------------------
0.00% 3.03% 0.00% 0.00% 0.00% 0x20 N/A 0 3603 3603:memstress 0xaaaac17c25ac 0 376 41 9314 2 [.] 0x00000000000025ac memstress memstress[25ac] 0{ 2 100.0% n/a}
0.00% 3.03% 0.00% 0.00% 0.00% 0x20 N/A 0 3603 3606:memstress 0xaaaac17c25ac 0 375 44 9155 1 [.] 0x00000000000025ac memstress memstress[25ac] 0{ 1 100.0% n/a}
0.00% 48.48% 0.00% 0.00% 0.00% 0x29 N/A 0 3603 3606:memstress 0xaaaac17c3e88 0 180 170 65 1 [.] 0x0000000000003e88 memstress memstress[3e88] 0{ 1 100.0% n/a}
0.00% 45.45% 0.00% 0.00% 0.00% 0x29 N/A 0 3603 3603:memstress 0xaaaac17c3e88 0 180 175 70 2 [.] 0x0000000000003e88 memstress memstress[3e88] 0{ 2 100.0% n/a}
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/builtin-c2c.c | 135 ++++++++++++++++++++++++++++-----------
1 file changed, 99 insertions(+), 36 deletions(-)
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index 725b23d9104b..1076bf8684d3 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -118,6 +118,7 @@ enum {
DISPLAY_LCL_HITM,
DISPLAY_RMT_HITM,
DISPLAY_TOT_HITM,
+ DISPLAY_SNP_PEER,
DISPLAY_MAX,
};
@@ -125,6 +126,7 @@ static const char *display_str[DISPLAY_MAX] = {
[DISPLAY_LCL_HITM] = "Local HITMs",
[DISPLAY_RMT_HITM] = "Remote HITMs",
[DISPLAY_TOT_HITM] = "Total HITMs",
+ [DISPLAY_SNP_PEER] = "Peer Snoop",
};
static const struct option c2c_options[] = {
@@ -822,6 +824,11 @@ static double percent_costly_snoop(struct c2c_hist_entry *c2c_he)
case DISPLAY_TOT_HITM:
st = stats->tot_hitm;
tot = total->tot_hitm;
+ break;
+ case DISPLAY_SNP_PEER:
+ st = stats->tot_peer;
+ tot = total->tot_peer;
+ break;
default:
break;
}
@@ -1229,6 +1236,10 @@ node_entry(struct perf_hpp_fmt *fmt __maybe_unused, struct perf_hpp *hpp,
ret = display_metrics(hpp, stats->tot_hitm,
c2c_he->stats.tot_hitm);
break;
+ case DISPLAY_SNP_PEER:
+ ret = display_metrics(hpp, stats->tot_peer,
+ c2c_he->stats.tot_peer);
+ break;
default:
break;
}
@@ -1609,6 +1620,7 @@ static struct c2c_header percent_costly_snoop_header[] = {
[DISPLAY_LCL_HITM] = HEADER_BOTH("Lcl", "Hitm"),
[DISPLAY_RMT_HITM] = HEADER_BOTH("Rmt", "Hitm"),
[DISPLAY_TOT_HITM] = HEADER_BOTH("Tot", "Hitm"),
+ [DISPLAY_SNP_PEER] = HEADER_BOTH("Peer", "Snoop"),
};
static struct c2c_dimension dim_percent_costly_snoop = {
@@ -2107,6 +2119,10 @@ static bool he__display(struct hist_entry *he, struct c2c_stats *stats)
he->filtered = filter_display(c2c_he->stats.tot_hitm,
stats->tot_hitm);
break;
+ case DISPLAY_SNP_PEER:
+ he->filtered = filter_display(c2c_he->stats.tot_peer,
+ stats->tot_peer);
+ break;
default:
break;
}
@@ -2135,6 +2151,8 @@ static inline bool is_valid_hist_entry(struct hist_entry *he)
case DISPLAY_TOT_HITM:
has_record = !!c2c_he->stats.tot_hitm;
break;
+ case DISPLAY_SNP_PEER:
+ has_record = !!c2c_he->stats.tot_peer;
default:
break;
}
@@ -2224,7 +2242,10 @@ static int resort_cl_cb(struct hist_entry *he, void *arg __maybe_unused)
}
static struct c2c_header header_node_0 = HEADER_LOW("Node");
-static struct c2c_header header_node_1 = HEADER_LOW("Node{cpus %hitms %stores}");
+static struct c2c_header header_node_1_hitms_stores =
+ HEADER_LOW("Node{cpus %hitms %stores}");
+static struct c2c_header header_node_1_peers_stores =
+ HEADER_LOW("Node{cpus %peers %stores}");
static struct c2c_header header_node_2 = HEADER_LOW("Node{cpu list}");
static void setup_nodes_header(void)
@@ -2234,7 +2255,10 @@ static void setup_nodes_header(void)
dim_node.header = header_node_0;
break;
case 1:
- dim_node.header = header_node_1;
+ if (c2c.display == DISPLAY_SNP_PEER)
+ dim_node.header = header_node_1_peers_stores;
+ else
+ dim_node.header = header_node_1_hitms_stores;
break;
case 2:
dim_node.header = header_node_2;
@@ -2308,13 +2332,14 @@ static int setup_nodes(struct perf_session *session)
}
#define HAS_HITMS(__h) ((__h)->stats.lcl_hitm || (__h)->stats.rmt_hitm)
+#define HAS_PEER(__h) ((__h)->stats.lcl_peer || (__h)->stats.rmt_peer)
static int resort_shared_cl_cb(struct hist_entry *he, void *arg __maybe_unused)
{
struct c2c_hist_entry *c2c_he;
c2c_he = container_of(he, struct c2c_hist_entry, he);
- if (HAS_HITMS(c2c_he)) {
+ if (HAS_HITMS(c2c_he) || HAS_PEER(c2c_he)) {
c2c.shared_clines++;
c2c_add_stats(&c2c.shared_clines_stats, &c2c_he->stats);
}
@@ -2447,13 +2472,22 @@ static void print_pareto(FILE *out)
int ret;
const char *cl_output;
- cl_output = "cl_num,"
- "cl_rmt_hitm,"
- "cl_lcl_hitm,"
- "cl_stores_l1hit,"
- "cl_stores_l1miss,"
- "cl_stores_na,"
- "dcacheline";
+ if (c2c.display != DISPLAY_SNP_PEER)
+ cl_output = "cl_num,"
+ "cl_rmt_hitm,"
+ "cl_lcl_hitm,"
+ "cl_stores_l1hit,"
+ "cl_stores_l1miss,"
+ "cl_stores_na,"
+ "dcacheline";
+ else
+ cl_output = "cl_num,"
+ "cl_rmt_peer,"
+ "cl_lcl_peer,"
+ "cl_stores_l1hit,"
+ "cl_stores_l1miss,"
+ "cl_stores_na,"
+ "dcacheline";
perf_hpp_list__init(&hpp_list);
ret = hpp_list__parse(&hpp_list, cl_output, NULL);
@@ -2852,6 +2886,8 @@ static int setup_display(const char *str)
c2c.display = DISPLAY_RMT_HITM;
else if (!strcmp(display, "lcl"))
c2c.display = DISPLAY_LCL_HITM;
+ else if (!strcmp(display, "peer"))
+ c2c.display = DISPLAY_SNP_PEER;
else {
pr_err("failed: unknown display type: %s\n", str);
return -1;
@@ -2898,10 +2934,12 @@ static int build_cl_output(char *cl_sort, bool no_source)
}
if (asprintf(&c2c.cl_output,
- "%s%s%s%s%s%s%s%s%s%s",
+ "%s%s%s%s%s%s%s%s%s%s%s%s",
c2c.use_stdio ? "cl_num_empty," : "",
- "percent_rmt_hitm,"
- "percent_lcl_hitm,"
+ c2c.display == DISPLAY_SNP_PEER ? "percent_rmt_peer,"
+ "percent_lcl_peer," :
+ "percent_rmt_hitm,"
+ "percent_lcl_hitm,",
"percent_stores_l1hit,"
"percent_stores_l1miss,"
"percent_stores_na,"
@@ -2909,8 +2947,10 @@ static int build_cl_output(char *cl_sort, bool no_source)
add_pid ? "pid," : "",
add_tid ? "tid," : "",
add_iaddr ? "iaddr," : "",
- "mean_rmt,"
- "mean_lcl,"
+ c2c.display == DISPLAY_SNP_PEER ? "mean_rmt_peer,"
+ "mean_lcl_peer," :
+ "mean_rmt,"
+ "mean_lcl,",
"mean_load,"
"tot_recs,"
"cpucnt,",
@@ -2931,6 +2971,7 @@ static int build_cl_output(char *cl_sort, bool no_source)
static int setup_coalesce(const char *coalesce, bool no_source)
{
const char *c = coalesce ?: coalesce_default;
+ const char *sort_str = NULL;
if (asprintf(&c2c.cl_sort, "offset,%s", c) < 0)
return -ENOMEM;
@@ -2938,12 +2979,16 @@ static int setup_coalesce(const char *coalesce, bool no_source)
if (build_cl_output(c2c.cl_sort, no_source))
return -1;
- if (asprintf(&c2c.cl_resort, "offset,%s",
- c2c.display == DISPLAY_TOT_HITM ?
- "tot_hitm" :
- c2c.display == DISPLAY_RMT_HITM ?
- "rmt_hitm,lcl_hitm" :
- "lcl_hitm,rmt_hitm") < 0)
+ if (c2c.display == DISPLAY_TOT_HITM)
+ sort_str = "tot_hitm";
+ else if (c2c.display == DISPLAY_RMT_HITM)
+ sort_str = "rmt_hitm,lcl_hitm";
+ else if (c2c.display == DISPLAY_LCL_HITM)
+ sort_str = "lcl_hitm,rmt_hitm";
+ else if (c2c.display == DISPLAY_SNP_PEER)
+ sort_str = "tot_peer";
+
+ if (asprintf(&c2c.cl_resort, "offset,%s", sort_str) < 0)
return -ENOMEM;
pr_debug("coalesce sort fields: %s\n", c2c.cl_sort);
@@ -2991,7 +3036,7 @@ static int perf_c2c__report(int argc, const char **argv)
"print_type,threshold[,print_limit],order,sort_key[,branch],value",
callchain_help, &parse_callchain_opt,
callchain_default_opt),
- OPT_STRING('d', "display", &display, "Switch HITM output type", "lcl,rmt"),
+ OPT_STRING('d', "display", &display, "Switch HITM output type", "tot,lcl,rmt,peer"),
OPT_STRING('c', "coalesce", &coalesce, "coalesce fields",
"coalesce fields: pid,tid,iaddr,dso"),
OPT_BOOLEAN('f', "force", &symbol_conf.force, "don't complain, do it"),
@@ -3082,20 +3127,36 @@ static int perf_c2c__report(int argc, const char **argv)
goto out_mem2node;
}
- output_str = "cl_idx,"
- "dcacheline,"
- "dcacheline_node,"
- "dcacheline_count,"
- "percent_costly_snoop,"
- "tot_hitm,lcl_hitm,rmt_hitm,"
- "tot_recs,"
- "tot_loads,"
- "tot_stores,"
- "stores_l1hit,stores_l1miss,stores_na,"
- "ld_fbhit,ld_l1hit,ld_l2hit,"
- "ld_lclhit,lcl_hitm,"
- "ld_rmthit,rmt_hitm,"
- "dram_lcl,dram_rmt";
+ if (c2c.display != DISPLAY_SNP_PEER)
+ output_str = "cl_idx,"
+ "dcacheline,"
+ "dcacheline_node,"
+ "dcacheline_count,"
+ "percent_costly_snoop,"
+ "tot_hitm,lcl_hitm,rmt_hitm,"
+ "tot_recs,"
+ "tot_loads,"
+ "tot_stores,"
+ "stores_l1hit,stores_l1miss,stores_na,"
+ "ld_fbhit,ld_l1hit,ld_l2hit,"
+ "ld_lclhit,lcl_hitm,"
+ "ld_rmthit,rmt_hitm,"
+ "dram_lcl,dram_rmt";
+ else
+ output_str = "cl_idx,"
+ "dcacheline,"
+ "dcacheline_node,"
+ "dcacheline_count,"
+ "percent_costly_snoop,"
+ "tot_peer,lcl_peer,rmt_peer,"
+ "tot_recs,"
+ "tot_loads,"
+ "tot_stores,"
+ "stores_l1hit,stores_l1miss,stores_na,"
+ "ld_fbhit,ld_l1hit,ld_l2hit,"
+ "ld_lclhit,lcl_hitm,"
+ "ld_rmthit,rmt_hitm,"
+ "dram_lcl,dram_rmt";
if (c2c.display == DISPLAY_TOT_HITM)
sort_str = "tot_hitm";
@@ -3103,6 +3164,8 @@ static int perf_c2c__report(int argc, const char **argv)
sort_str = "rmt_hitm";
else if (c2c.display == DISPLAY_LCL_HITM)
sort_str = "lcl_hitm";
+ else if (c2c.display == DISPLAY_SNP_PEER)
+ sort_str = "tot_peer";
c2c_hists__reinit(&c2c.hists, output_str, sort_str);
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 11/12] perf c2c: Use 'peer' as default display for Arm64
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (9 preceding siblings ...)
2022-05-30 11:40 ` [PATCH v4 10/12] perf c2c: Sort on peer snooping for load operations Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-30 11:40 ` [PATCH v4 12/12] perf c2c: Update documentation for new display option 'peer' Leo Yan
` (2 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
Since Arm64 arch doesn't support HITMs flags, this patch changes to use
'peer' as default display if user doesn't specify any type; for other
arches, it still uses 'tot' as default display type if user doesn't
specify it.
This patch changes to call perf_session__new() in an earlier place, so
session environment can be initialized ahead and arch info can be used
for setting display type.
Suggested-by: Ali Saidi <alisaidi@amazon.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/builtin-c2c.c | 36 ++++++++++++++++++++++++------------
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index 1076bf8684d3..ccfd23103b96 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -2878,7 +2878,7 @@ static int setup_callchain(struct evlist *evlist)
static int setup_display(const char *str)
{
- const char *display = str ?: "tot";
+ const char *display = str;
if (!strcmp(display, "tot"))
c2c.display = DISPLAY_TOT_HITM;
@@ -3066,27 +3066,39 @@ static int perf_c2c__report(int argc, const char **argv)
data.path = input_name;
data.force = symbol_conf.force;
+ session = perf_session__new(&data, &c2c.tool);
+ if (IS_ERR(session)) {
+ err = PTR_ERR(session);
+ pr_debug("Error creating perf session\n");
+ goto out;
+ }
+
+ /*
+ * Use the 'tot' as default display type if user doesn't specify it;
+ * since Arm64 platform doesn't support HITMs flag, use 'peer' as the
+ * default display type.
+ */
+ if (!display) {
+ if (!strcmp(perf_env__arch(&session->header.env), "arm64"))
+ display = "peer";
+ else
+ display = "tot";
+ }
+
err = setup_display(display);
if (err)
- goto out;
+ goto out_session;
err = setup_coalesce(coalesce, no_source);
if (err) {
pr_debug("Failed to initialize hists\n");
- goto out;
+ goto out_session;
}
err = c2c_hists__init(&c2c.hists, "dcacheline", 2);
if (err) {
pr_debug("Failed to initialize hists\n");
- goto out;
- }
-
- session = perf_session__new(&data, &c2c.tool);
- if (IS_ERR(session)) {
- err = PTR_ERR(session);
- pr_debug("Error creating perf session\n");
- goto out;
+ goto out_session;
}
session->itrace_synth_opts = &itrace_synth_opts;
@@ -3094,7 +3106,7 @@ static int perf_c2c__report(int argc, const char **argv)
err = setup_nodes(session);
if (err) {
pr_err("Failed setup nodes\n");
- goto out;
+ goto out_session;
}
err = mem2node__init(&c2c.mem2node, &session->header.env);
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v4 12/12] perf c2c: Update documentation for new display option 'peer'
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (10 preceding siblings ...)
2022-05-30 11:40 ` [PATCH v4 11/12] perf c2c: Use 'peer' as default display for Arm64 Leo Yan
@ 2022-05-30 11:40 ` Leo Yan
2022-05-31 18:44 ` [PATCH v4 00/12] perf c2c: Support display for Arm64 Joe Mario
2022-06-03 19:33 ` Arnaldo Carvalho de Melo
13 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-05-30 11:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei,
Joe Mario, Adam Li, German Gomez, James Clark, Ali Saidi,
linux-perf-users, linux-kernel
Cc: Leo Yan
Since the new display option 'peer' is introduced, this patch is to
update the documentation to reflect it.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/Documentation/perf-c2c.txt | 30 ++++++++++++++++++++-------
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/tools/perf/Documentation/perf-c2c.txt b/tools/perf/Documentation/perf-c2c.txt
index 6f69173731aa..e1549798c6f3 100644
--- a/tools/perf/Documentation/perf-c2c.txt
+++ b/tools/perf/Documentation/perf-c2c.txt
@@ -109,7 +109,8 @@ REPORT OPTIONS
-d::
--display::
- Switch to HITM type (rmt, lcl) to display and sort on. Total HITMs as default.
+ Switch to HITM type (rmt, lcl) or peer snooping type (peer) to display
+ and sort on. Total HITMs (tot) as default.
--stitch-lbr::
Show callgraph with stitched LBRs, which may have more complete
@@ -174,12 +175,18 @@ For each cacheline in the 1) list we display following data:
Cacheline
- cacheline address (hex number)
- Rmt/Lcl Hitm
+ Rmt/Lcl Hitm (Display with HITM types)
- cacheline percentage of all Remote/Local HITM accesses
- LLC Load Hitm - Total, LclHitm, RmtHitm
+ Peer Snoop (Display with peer type)
+ - cacheline percentage of all peer accesses
+
+ LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types)
- count of Total/Local/Remote load HITMs
+ Load Peer - Total, Local, Remote (For display with peer type)
+ - count of Total/Local/Remote load from peer cache or DRAM
+
Total records
- sum of all cachelines accesses
@@ -201,16 +208,21 @@ For each cacheline in the 1) list we display following data:
- count of LLC load accesses, includes LLC hits and LLC HITMs
RMT Load Hit - RmtHit, RmtHitm
- - count of remote load accesses, includes remote hits and remote HITMs
+ - count of remote load accesses, includes remote hits and remote HITMs;
+ on Arm neoverse cores, RmtHit is used to account remote accesses,
+ includes remote DRAM or any upward cache level in remote node
Load Dram - Lcl, Rmt
- count of local and remote DRAM accesses
For each offset in the 2) list we display following data:
- HITM - Rmt, Lcl
+ HITM - Rmt, Lcl (Display with HITM types)
- % of Remote/Local HITM accesses for given offset within cacheline
+ Peer Snoop - Rmt, Lcl (Display with peer type)
+ - % of Remote/Local peer accesses for given offset within cacheline
+
Store Refs - L1 Hit, L1 Miss, N/A
- % of store accesses that hit L1, missed L1 and N/A (no available) memory
level for given offset within cacheline
@@ -227,9 +239,12 @@ For each offset in the 2) list we display following data:
Code address
- code address responsible for the accesses
- cycles - rmt hitm, lcl hitm, load
+ cycles - rmt hitm, lcl hitm, load (Display with HITM types)
- sum of cycles for given accesses - Remote/Local HITM and generic load
+ cycles - rmt peer, lcl peer, load (Display with peer type)
+ - sum of cycles for given accesses - Remote/Local peer load and generic load
+
cpu cnt
- number of cpus that participated on the access
@@ -251,7 +266,8 @@ The 'Node' field displays nodes that accesses given cacheline
offset. Its output comes in 3 flavors:
- node IDs separated by ','
- node IDs with stats for each ID, in following format:
- Node{cpus %hitms %stores}
+ Node{cpus %hitms %stores} (Display with HITM types)
+ Node{cpus %peers %stores} (Display with peer type)
- node IDs with list of affected CPUs in following format:
Node{cpu list}
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v4 00/12] perf c2c: Support display for Arm64
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (11 preceding siblings ...)
2022-05-30 11:40 ` [PATCH v4 12/12] perf c2c: Update documentation for new display option 'peer' Leo Yan
@ 2022-05-31 18:44 ` Joe Mario
2022-06-01 10:25 ` Leo Yan
2022-06-03 19:33 ` Arnaldo Carvalho de Melo
13 siblings, 1 reply; 21+ messages in thread
From: Joe Mario @ 2022-05-31 18:44 UTC (permalink / raw)
To: Leo Yan, Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei, Adam Li,
German Gomez, James Clark, Ali Saidi, linux-perf-users,
linux-kernel
On 5/30/22 7:40 AM, Leo Yan wrote:
> Arm64 Neoverse CPUs supports data source in Arm SPE trace, this allows
> us to detect cache line contention and transfers.
>
> This patch set is based on Ali Said's patch set v9 "perf: arm-spe: Decode SPE
> source and use for perf c2c" [1] and Ali's patch set doesn't need any
> change in this new round.
>
> To clearly show peer loads and express the local peer loads and remote
> peer lodes, this patch introduces three new metrics 'lcl_peer',
> 'rmt_peer' and 'tot_peer'. The display 'peer' mode uses metric
> 'tot_peer' for sorting cache lines.
>
> Patches 01-05 adds statistics for memory samples, and add dimensions for
> peer metrics.
>
> Patches 06-09 are for refactoring, it refines the code with more general
> naming so this can allow us to easier to extend display modes but not
> strictly bound to HITM tags.
>
> Patches 10-11 are to extend display 'peer' mode, and also changes to use
> 'peer' mode as default mode for Arm64 arches.
>
> Patch 12 updates document to describe the new dimensions for peer
> metrics.
>
> This patch set has been verified for both x86 and Arm64 memory samples.
>
> Known issues: Joe reminded there have an issue in patch set v3 that the
> cache line metric shows 'N/A' for node, this is because Arm SPE trace
> data doesn't contain physical address and leads to perf c2c tool fails
> to find matched node range if physical address is zero. This issue is
> addressed in a separte patch [2]. Since I am still using the old
> perf data file (I have no Neoverse platforms), the output result still
> shows the Node field is 'N/A'.
>
Hi Leo:
I built a new perf with your patches and ran it on a 2-numa node Neoverse platform.
I then ran my simple test that creates reader and writer threads to tug on the same cacheline.
The c2c output is appended below.
The output looks good, especially where you've broken out the (average) cycles for local and remote peer loads.
And I'm glad to see you fixed the "Node" column. I use that a lot to help detect remote node accesses.
And the "PA cnt" field is working as well, which is important to see if numa_balance is moving the data around.
=================================================
Shared Data Cache Line Table
=================================================
#
# ----------- Cacheline ---------- Peer ------- Load Peer ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ----
# Index Address Node PA cnt Snoop Total Local Remote records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt
# ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........
#
0 0x422140 0 6904 74.86% 137 131 6 148008 144970 3038 0 0 3038 0 144833 120 11 0 6 0 0 0
1 0xffffd976e63ae5c0 1 6 3.83% 7 7 0 15 15 0 0 0 0 0 8 4 3 0 0 0 0 0
2 0xffff07ffbf290980 0 5 2.19% 4 2 2 14 14 0 0 0 0 0 10 1 1 0 2 0 0 0
3 0xffffd976e57275c0 1 1 0.55% 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0
4 0xffffd976e6071c00 1 3 0.55% 1 0 1 4 4 0 0 0 0 0 3 0 0 0 1 0 0 0
[snip]
=================================================
Shared Cache Line Distribution Pareto
=================================================
#
# -- Peer Snoop -- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared
# Num Rmt Lcl L1 Hit L1 Miss N/A Offset Node PA cnt Code address rmt peer lcl peer load records cnt Symbol Object Source:Line Node
# ..... ....... ....... ....... ....... ....... .................. .... ...... .................. ........ ........ ........ ....... ........ .......................... ....... ......................... ....
#
----------------------------------------------------------------------
0 6 131 0 0 3038 0x422140
----------------------------------------------------------------------
0.00% 0.00% 0.00% 0.00% 52.60% 0x8 0 1 0x400e6c 0 0 0 1598 4 [.] writer tugtest tugtest.c:152 0 1
0.00% 0.00% 0.00% 0.00% 47.40% 0x10 0 1 0x400e7c 0 0 0 1440 4 [.] writer tugtest tugtest.c:153 0 1
33.33% 75.57% 0.00% 0.00% 0.00% 0x20 0 1 0x401018 4095 3803 3419 409 4 [.] reader tugtest tugtest.c:187 0 1
66.67% 24.43% 0.00% 0.00% 0.00% 0x28 0 1 0x401034 4095 3470 3643 413 4 [.] reader tugtest tugtest.c:187 0 1
----------------------------------------------------------------------
1 0 7 0 0 0 0xffffd976e63ae5c0
----------------------------------------------------------------------
0.00% 57.14% 0.00% 0.00% 0.00% 0x0 1 1 0xffffd976e4815fbc 0 1333 0 4 2 [k] ktime_get [kernel.kallsyms] seqlock.h:276 1
0.00% 14.29% 0.00% 0.00% 0.00% 0x0 1 1 0xffffd976e4816d10 0 266 794 4 3 [k] ktime_get_update_offsets_n [kernel.kallsyms] seqlock.h:276 0 1
0.00% 28.57% 0.00% 0.00% 0.00% 0x30 1 1 0xffffd976e4816d20 0 87 150 4 3 [k] ktime_get_update_offsets_n [kernel.kallsyms] timekeeping.c:2298 0 1
----------------------------------------------------------------------
2 2 2 0 0 0 0xffff07ffbf290980
----------------------------------------------------------------------
50.00% 100.00% 0.00% 0.00% 0.00% 0x4 0 1 0xffffd976e47d2bdc 1217 1600 1147 4 3 [k] queued_spin_lock_slowpath [kernel.kallsyms] qspinlock.c:511 0 1
50.00% 0.00% 0.00% 0.00% 0.00% 0x4 0 1 0xffffd976e47d2a2c 4033 0 0 1 1 [k] queued_spin_lock_slowpath [kernel.kallsyms] qspinlock.c:382 0 1
----------------------------------------------------------------------
Thanks for doing this. It looks good.
I'll assume someone else is reviewing your code changes.
Joe
> Another thing is we need to enhance data source setting for old Arm
> platforms. As discussed, German would follow up this task later.
>
> The latest patch set has been uploaded on the git server [3].
>
> The display result with x86 memory samples:
>
> =================================================
> Shared Data Cache Line Table
> =================================================
> #
> # ----------- Cacheline ---------- Tot ------- Load Hitm ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ----
> # Index Address Node PA cnt Hitm Total LclHitm RmtHitm records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt
> # ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........
> #
> 0 0x55c8971f0080 0 1967 66.14% 252 252 0 6044 3550 2494 2024 470 0 528 2672 78 20 252 0 0 0 0
> 1 0x55c8971f00c0 0 1 33.86% 129 129 0 914 914 0 0 0 0 272 374 52 87 129 0 0 0 0
>
> =================================================
> Shared Cache Line Distribution Pareto
> =================================================
> #
> # ----- HITM ----- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared
> # Num RmtHitm LclHitm L1 Hit L1 Miss N/A Offset Node PA cnt Code address rmt hitm lcl hitm load records cnt Symbol Object Source:Line Node
> # ..... ....... ....... ....... ....... ....... .................. .... ...... .................. ........ ........ ........ ....... ........ ...................... ................. ....................... ....
> #
> ----------------------------------------------------------------------
> 0 0 252 2024 470 0 0x55c8971f0080
> ----------------------------------------------------------------------
> 0.00% 12.30% 0.00% 0.00% 0.00% 0x0 0 1 0x55c8971ed3e9 0 1313 863 1222 3 [.] 0x00000000000013e9 false_sharing.exe false_sharing.exe[13e9] 0
> 0.00% 0.79% 90.51% 0.00% 0.00% 0x0 0 1 0x55c8971ed3e2 0 1800 878 3029 3 [.] 0x00000000000013e2 false_sharing.exe false_sharing.exe[13e2] 0
> 0.00% 0.00% 9.49% 100.00% 0.00% 0x0 0 1 0x55c8971ed3f4 0 0 0 662 3 [.] 0x00000000000013f4 false_sharing.exe false_sharing.exe[13f4] 0
> 0.00% 86.90% 0.00% 0.00% 0.00% 0x20 0 1 0x55c8971ed447 0 141 103 1131 2 [.] 0x0000000000001447 false_sharing.exe false_sharing.exe[1447] 0
>
> ----------------------------------------------------------------------
> 1 0 129 0 0 0 0x55c8971f00c0
> ----------------------------------------------------------------------
> 0.00% 100.00% 0.00% 0.00% 0.00% 0x20 0 1 0x55c8971ed455 0 88 94 914 2 [.] 0x0000000000001455 false_sharing.exe false_sharing.exe[1455] 0
>
>
> The display result with Arm SPE:
>
> =================================================
> Shared Data Cache Line Table
> =================================================
> #
> # ----------- Cacheline ---------- Peer ------- Load Peer ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ----
> # Index Address Node PA cnt Snoop Total Local Remote records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt
> # ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........
> #
> 0 0xaaaac17d6000 N/A 0 100.00% 99 99 0 18851 18851 0 0 0 0 0 18752 0 99 0 0 0 0 0
>
> =================================================
> Shared Cache Line Distribution Pareto
> =================================================
> #
> # -- Peer Snoop -- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared
> # Num Rmt Lcl L1 Hit L1 Miss N/A Offset Node PA cnt Code address rmt peer lcl peer load records cnt Symbol Object Source:Line Node{cpus %peers %stores}
> # ..... ....... ....... ....... ....... ....... .................. .... ...... .................. ........ ........ ........ ....... ........ ...................... ................ ............... ....
> #
> ----------------------------------------------------------------------
> 0 0 99 0 0 0 0xaaaac17d6000
> ----------------------------------------------------------------------
> 0.00% 6.06% 0.00% 0.00% 0.00% 0x20 N/A 0 0xaaaac17c25ac 0 375 43 18469 2 [.] 0x00000000000025ac memstress memstress[25ac] 0{ 2 100.0% n/a}
> 0.00% 93.94% 0.00% 0.00% 0.00% 0x29 N/A 0 0xaaaac17c3e88 0 180 173 135 2 [.] 0x0000000000003e88 memstress memstress[3e88] 0{ 2 100.0% n/a}
>
>
> Changes from v3:
> * Changed to display remote and local peer accesses (Joe);
> * Fixed the usage info for display types (Joe);
> * Do not display HITM dimensions when use 'peer' display, and HITM
> display doesn't show any 'peer' dimensions (James);
> * Split to smaller patches for adding dimensions of peer operations;
> * Updated documentation to reflect the latest GUI and stdio.
>
> Changes from v2:
> * Updated patch 04 to account metrics for both cache level and ld_peer
> for PEER flag;
> * Updated document for metric 'rmt_hit' which is accounted for all
> remote accesses (include remote DRAM and any upward caches).
>
> Changes from v1:
> * Updated patches 01, 02 and 03 to support 'N/A' metrics for store
> operations, so can align with the patch set [1] for store samples.
>
>
> [1] https://lore.kernel.org/lkml/20220517020326.18580-1-alisaidi@amazon.com/
> [2] https://lore.kernel.org/lkml/20220530083645.253432-1-leo.yan@linaro.org/
> [3] https://git.linaro.org/people/leo.yan/linux-spe.git/ branch: perf_c2c_arm_spe_peer_v4
>
>
> Leo Yan (12):
> perf mem: Add statistics for peer snooping
> perf c2c: Output statistics for peer snooping
> perf c2c: Add dimensions for peer load operations
> perf c2c: Add dimensions of peer metrics for cache line view
> perf c2c: Add mean dimensions for peer operations
> perf c2c: Use explicit names for display macros
> perf c2c: Rename dimension from 'percent_hitm' to
> 'percent_costly_snoop'
> perf c2c: Refactor node header
> perf c2c: Refactor display string
> perf c2c: Sort on peer snooping for load operations
> perf c2c: Use 'peer' as default display for Arm64
> perf c2c: Update documentation for new display option 'peer'
>
> tools/perf/Documentation/perf-c2c.txt | 30 +-
> tools/perf/builtin-c2c.c | 454 ++++++++++++++++++++------
> tools/perf/util/mem-events.c | 28 +-
> tools/perf/util/mem-events.h | 3 +
> 4 files changed, 403 insertions(+), 112 deletions(-)
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 00/12] perf c2c: Support display for Arm64
2022-05-31 18:44 ` [PATCH v4 00/12] perf c2c: Support display for Arm64 Joe Mario
@ 2022-06-01 10:25 ` Leo Yan
2022-06-02 16:59 ` Ian Rogers
2022-06-02 17:11 ` Ali Saidi
0 siblings, 2 replies; 21+ messages in thread
From: Leo Yan @ 2022-06-01 10:25 UTC (permalink / raw)
To: Joe Mario
Cc: Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Ian Rogers, Like Xu, Kajol Jain, Li Huafei, Adam Li,
German Gomez, James Clark, Ali Saidi, linux-perf-users,
linux-kernel
Hi Joe,
On Tue, May 31, 2022 at 02:44:07PM -0400, Joe Mario wrote:
[...]
> Hi Leo:
> I built a new perf with your patches and ran it on a 2-numa node Neoverse platform.
> I then ran my simple test that creates reader and writer threads to tug on the same cacheline.
> The c2c output is appended below.
>
> The output looks good, especially where you've broken out the (average) cycles for local and remote peer loads.
> And I'm glad to see you fixed the "Node" column. I use that a lot to help detect remote node accesses.
Thanks a lot for your testing and suggestions, which are really helpful!
> And the "PA cnt" field is working as well, which is important to see if numa_balance is moving the data around.
Good to know this. To be honest, before I didn't note for "PA cnt"
metric, I checked a bit for the code, this metrics is very useful to
understand how it's severe that a cache line is accessed from different
addresses, so we can get sense how a cache line is hammered.
> =================================================
> Shared Data Cache Line Table
> =================================================
> #
> # ----------- Cacheline ---------- Peer ------- Load Peer ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ----
> # Index Address Node PA cnt Snoop Total Local Remote records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt
> # ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........
> #
> 0 0x422140 0 6904 74.86% 137 131 6 148008 144970 3038 0 0 3038 0 144833 120 11 0 6 0 0 0
> 1 0xffffd976e63ae5c0 1 6 3.83% 7 7 0 15 15 0 0 0 0 0 8 4 3 0 0 0 0 0
> 2 0xffff07ffbf290980 0 5 2.19% 4 2 2 14 14 0 0 0 0 0 10 1 1 0 2 0 0 0
> 3 0xffffd976e57275c0 1 1 0.55% 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0
> 4 0xffffd976e6071c00 1 3 0.55% 1 0 1 4 4 0 0 0 0 0 3 0 0 0 1 0 0 0
> [snip]
> =================================================
> Shared Cache Line Distribution Pareto
> =================================================
> #
> # -- Peer Snoop -- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared
> # Num Rmt Lcl L1 Hit L1 Miss N/A Offset Node PA cnt Code address rmt peer lcl peer load records cnt Symbol Object Source:Line Node
> # ..... ....... ....... ....... ....... ....... .................. .... ...... .................. ........ ........ ........ ....... ........ .......................... ....... ......................... ....
> #
> ----------------------------------------------------------------------
> 0 6 131 0 0 3038 0x422140
> ----------------------------------------------------------------------
> 0.00% 0.00% 0.00% 0.00% 52.60% 0x8 0 1 0x400e6c 0 0 0 1598 4 [.] writer tugtest tugtest.c:152 0 1
> 0.00% 0.00% 0.00% 0.00% 47.40% 0x10 0 1 0x400e7c 0 0 0 1440 4 [.] writer tugtest tugtest.c:153 0 1
> 33.33% 75.57% 0.00% 0.00% 0.00% 0x20 0 1 0x401018 4095 3803 3419 409 4 [.] reader tugtest tugtest.c:187 0 1
> 66.67% 24.43% 0.00% 0.00% 0.00% 0x28 0 1 0x401034 4095 3470 3643 413 4 [.] reader tugtest tugtest.c:187 0 1
>
> ----------------------------------------------------------------------
> 1 0 7 0 0 0 0xffffd976e63ae5c0
> ----------------------------------------------------------------------
> 0.00% 57.14% 0.00% 0.00% 0.00% 0x0 1 1 0xffffd976e4815fbc 0 1333 0 4 2 [k] ktime_get [kernel.kallsyms] seqlock.h:276 1
> 0.00% 14.29% 0.00% 0.00% 0.00% 0x0 1 1 0xffffd976e4816d10 0 266 794 4 3 [k] ktime_get_update_offsets_n [kernel.kallsyms] seqlock.h:276 0 1
> 0.00% 28.57% 0.00% 0.00% 0.00% 0x30 1 1 0xffffd976e4816d20 0 87 150 4 3 [k] ktime_get_update_offsets_n [kernel.kallsyms] timekeeping.c:2298 0 1
>
> ----------------------------------------------------------------------
> 2 2 2 0 0 0 0xffff07ffbf290980
> ----------------------------------------------------------------------
> 50.00% 100.00% 0.00% 0.00% 0.00% 0x4 0 1 0xffffd976e47d2bdc 1217 1600 1147 4 3 [k] queued_spin_lock_slowpath [kernel.kallsyms] qspinlock.c:511 0 1
> 50.00% 0.00% 0.00% 0.00% 0.00% 0x4 0 1 0xffffd976e47d2a2c 4033 0 0 1 1 [k] queued_spin_lock_slowpath [kernel.kallsyms] qspinlock.c:382 0 1
>
> ----------------------------------------------------------------------
>
> Thanks for doing this. It looks good.
You are welcome! And very appreicate your helping to mature the code.
> I'll assume someone else is reviewing your code changes.
Yeah, let's give a bit more time for reviewing.
Thanks,
Leo
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 00/12] perf c2c: Support display for Arm64
2022-06-01 10:25 ` Leo Yan
@ 2022-06-02 16:59 ` Ian Rogers
2022-06-03 3:36 ` Leo Yan
2022-06-02 17:11 ` Ali Saidi
1 sibling, 1 reply; 21+ messages in thread
From: Ian Rogers @ 2022-06-02 16:59 UTC (permalink / raw)
To: Leo Yan
Cc: Joe Mario, Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Like Xu, Kajol Jain, Li Huafei, Adam Li,
German Gomez, James Clark, Ali Saidi, linux-perf-users,
linux-kernel
On Wed, Jun 1, 2022 at 3:25 AM Leo Yan <leo.yan@linaro.org> wrote:
>
> Hi Joe,
>
> On Tue, May 31, 2022 at 02:44:07PM -0400, Joe Mario wrote:
>
> [...]
>
> > Hi Leo:
> > I built a new perf with your patches and ran it on a 2-numa node Neoverse platform.
> > I then ran my simple test that creates reader and writer threads to tug on the same cacheline.
> > The c2c output is appended below.
> >
> > The output looks good, especially where you've broken out the (average) cycles for local and remote peer loads.
> > And I'm glad to see you fixed the "Node" column. I use that a lot to help detect remote node accesses.
>
> Thanks a lot for your testing and suggestions, which are really helpful!
>
> > And the "PA cnt" field is working as well, which is important to see if numa_balance is moving the data around.
>
> Good to know this. To be honest, before I didn't note for "PA cnt"
> metric, I checked a bit for the code, this metrics is very useful to
> understand how it's severe that a cache line is accessed from different
> addresses, so we can get sense how a cache line is hammered.
>
> > =================================================
> > Shared Data Cache Line Table
> > =================================================
> > #
> > # ----------- Cacheline ---------- Peer ------- Load Peer ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ----
> > # Index Address Node PA cnt Snoop Total Local Remote records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt
> > # ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........
> > #
> > 0 0x422140 0 6904 74.86% 137 131 6 148008 144970 3038 0 0 3038 0 144833 120 11 0 6 0 0 0
> > 1 0xffffd976e63ae5c0 1 6 3.83% 7 7 0 15 15 0 0 0 0 0 8 4 3 0 0 0 0 0
> > 2 0xffff07ffbf290980 0 5 2.19% 4 2 2 14 14 0 0 0 0 0 10 1 1 0 2 0 0 0
> > 3 0xffffd976e57275c0 1 1 0.55% 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0
> > 4 0xffffd976e6071c00 1 3 0.55% 1 0 1 4 4 0 0 0 0 0 3 0 0 0 1 0 0 0
> > [snip]
> > =================================================
> > Shared Cache Line Distribution Pareto
> > =================================================
> > #
> > # -- Peer Snoop -- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared
> > # Num Rmt Lcl L1 Hit L1 Miss N/A Offset Node PA cnt Code address rmt peer lcl peer load records cnt Symbol Object Source:Line Node
> > # ..... ....... ....... ....... ....... ....... .................. .... ...... .................. ........ ........ ........ ....... ........ .......................... ....... ......................... ....
> > #
> > ----------------------------------------------------------------------
> > 0 6 131 0 0 3038 0x422140
> > ----------------------------------------------------------------------
> > 0.00% 0.00% 0.00% 0.00% 52.60% 0x8 0 1 0x400e6c 0 0 0 1598 4 [.] writer tugtest tugtest.c:152 0 1
> > 0.00% 0.00% 0.00% 0.00% 47.40% 0x10 0 1 0x400e7c 0 0 0 1440 4 [.] writer tugtest tugtest.c:153 0 1
> > 33.33% 75.57% 0.00% 0.00% 0.00% 0x20 0 1 0x401018 4095 3803 3419 409 4 [.] reader tugtest tugtest.c:187 0 1
> > 66.67% 24.43% 0.00% 0.00% 0.00% 0x28 0 1 0x401034 4095 3470 3643 413 4 [.] reader tugtest tugtest.c:187 0 1
> >
> > ----------------------------------------------------------------------
> > 1 0 7 0 0 0 0xffffd976e63ae5c0
> > ----------------------------------------------------------------------
> > 0.00% 57.14% 0.00% 0.00% 0.00% 0x0 1 1 0xffffd976e4815fbc 0 1333 0 4 2 [k] ktime_get [kernel.kallsyms] seqlock.h:276 1
> > 0.00% 14.29% 0.00% 0.00% 0.00% 0x0 1 1 0xffffd976e4816d10 0 266 794 4 3 [k] ktime_get_update_offsets_n [kernel.kallsyms] seqlock.h:276 0 1
> > 0.00% 28.57% 0.00% 0.00% 0.00% 0x30 1 1 0xffffd976e4816d20 0 87 150 4 3 [k] ktime_get_update_offsets_n [kernel.kallsyms] timekeeping.c:2298 0 1
> >
> > ----------------------------------------------------------------------
> > 2 2 2 0 0 0 0xffff07ffbf290980
> > ----------------------------------------------------------------------
> > 50.00% 100.00% 0.00% 0.00% 0.00% 0x4 0 1 0xffffd976e47d2bdc 1217 1600 1147 4 3 [k] queued_spin_lock_slowpath [kernel.kallsyms] qspinlock.c:511 0 1
> > 50.00% 0.00% 0.00% 0.00% 0.00% 0x4 0 1 0xffffd976e47d2a2c 4033 0 0 1 1 [k] queued_spin_lock_slowpath [kernel.kallsyms] qspinlock.c:382 0 1
> >
> > ----------------------------------------------------------------------
> >
> > Thanks for doing this. It looks good.
>
> You are welcome! And very appreicate your helping to mature the code.
>
> > I'll assume someone else is reviewing your code changes.
>
> Yeah, let's give a bit more time for reviewing.
>
> Thanks,
> Leo
This is great Leo! I've not been able to test the changes but I didn't
have any coding comments (happy to give an Acked-by). Do you think we
can add a test for this? The test can skip when c2c isn't supported.
Thanks,
Ian
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 00/12] perf c2c: Support display for Arm64
2022-06-01 10:25 ` Leo Yan
2022-06-02 16:59 ` Ian Rogers
@ 2022-06-02 17:11 ` Ali Saidi
2022-06-03 3:46 ` Leo Yan
1 sibling, 1 reply; 21+ messages in thread
From: Ali Saidi @ 2022-06-02 17:11 UTC (permalink / raw)
To: leo.yan
Cc: acme, peterz, mingo, mark.rutland, alexander.shishkin, jolsa,
namhyung, hi, irogers, likexu, kjain, lihuafei1, adam.li,
german.gomez, james.clark, alisaidi, linux-perf-users,
linux-kernel
Hi Leo,
On Wed, 1 Jun 2022 18:25:05 +0800 Leo Yan wrote:
> Hi Joe,
>
> On Tue, May 31, 2022 at 02:44:07PM -0400, Joe Mario wrote:
>
> [...]
>
> > Hi Leo:
> > I built a new perf with your patches and ran it on a 2-numa node Neoverse platform.
> > I then ran my simple test that creates reader and writer threads to tug on the same cacheline.
> > The c2c output is appended below.
> >
> > The output looks good, especially where you've broken out the (average) cycles for local and remote peer loads.
> > And I'm glad to see you fixed the "Node" column. I use that a lot to help detect remote node accesses.
>
> Thanks a lot for your testing and suggestions, which are really helpful!
>
> > And the "PA cnt" field is working as well, which is important to see if numa_balance is moving the data around.
>
> Good to know this. To be honest, before I didn't note for "PA cnt"
> metric, I checked a bit for the code, this metrics is very useful to
> understand how it's severe that a cache line is accessed from different
> addresses, so we can get sense how a cache line is hammered.
>
> [...]
>
> > Thanks for doing this. It looks good.
>
> You are welcome! And very appreicate your helping to mature the code.
Seconding that, thanks for progressing this so much Leo.
>
> > I'll assume someone else is reviewing your code changes.
>
> Yeah, let's give a bit more time for reviewing.
I've tested and given each patch a close look. I haven't found anything that
looks to change other architectures and the output on my Graviton systems looks
great. I pulled in your patch to add physical addresses to the spe records and
as expected I saw the Node properly populated and PA cnt is no longer zero. One
nit is the documentation still says that "Total HITMs (tot) as default," while
the code now defaults to "peer" on arm64. Other than that:
Tested-by: Ali Saidi <alisaidi@amazon.com>
Reviewed-by: Ali Saidi <alisaidi@amazon.com>
Thanks,
Ali
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 00/12] perf c2c: Support display for Arm64
2022-06-02 16:59 ` Ian Rogers
@ 2022-06-03 3:36 ` Leo Yan
0 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-06-03 3:36 UTC (permalink / raw)
To: Ian Rogers
Cc: Joe Mario, Arnaldo Carvalho de Melo, Peter Zijlstra, Ingo Molnar,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Alyssa Ross, Like Xu, Kajol Jain, Li Huafei, Adam Li,
German Gomez, James Clark, Ali Saidi, linux-perf-users,
linux-kernel
Hi Ian,
On Thu, Jun 02, 2022 at 09:59:29AM -0700, Ian Rogers wrote:
[...]
> This is great Leo! I've not been able to test the changes but I didn't
> have any coding comments (happy to give an Acked-by). Do you think we
> can add a test for this? The test can skip when c2c isn't supported.
It would be great if recieve your ACK tags :)
Yeah, agree that it's good thing to add test for perf c2c. Just note,
after rough thinkіng, seems to me the right thing to do is to add a
testing shell script in the folder tests/shell and use a tiny
multi-threading program for accessing the share cache line from
different nodes (or rollback to different CPUs).
I would like to use a separate patch for adding the test case, this
would be easier for upstreaming current patch set.
Please let me know if this is fine for you or not. Thanks for reviewing
and suggestions!
Leo
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 00/12] perf c2c: Support display for Arm64
2022-06-02 17:11 ` Ali Saidi
@ 2022-06-03 3:46 ` Leo Yan
0 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-06-03 3:46 UTC (permalink / raw)
To: Ali Saidi
Cc: acme, peterz, mingo, mark.rutland, alexander.shishkin, jolsa,
namhyung, hi, irogers, likexu, kjain, lihuafei1, adam.li,
german.gomez, james.clark, linux-perf-users, linux-kernel
On Thu, Jun 02, 2022 at 05:11:20PM +0000, Ali Saidi wrote:
[...]
> > You are welcome! And very appreicate your helping to mature the code.
>
> Seconding that, thanks for progressing this so much Leo.
You are very welcome, Ali!
> > > I'll assume someone else is reviewing your code changes.
> >
> > Yeah, let's give a bit more time for reviewing.
>
> I've tested and given each patch a close look. I haven't found anything that
> looks to change other architectures and the output on my Graviton systems looks
> great. I pulled in your patch to add physical addresses to the spe records and
> as expected I saw the Node properly populated and PA cnt is no longer zero. One
> nit is the documentation still says that "Total HITMs (tot) as default," while
> the code now defaults to "peer" on arm64. Other than that:
>
> Tested-by: Ali Saidi <alisaidi@amazon.com>
> Reviewed-by: Ali Saidi <alisaidi@amazon.com>
Thanks a lot for the testing. Will respin a new patch set for
correcting the documentation:
"Total HITMs (tot) as default, except Arm64 uses peer mode as default".
And will add your test and review tags.
Thanks,
Leo
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 00/12] perf c2c: Support display for Arm64
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
` (12 preceding siblings ...)
2022-05-31 18:44 ` [PATCH v4 00/12] perf c2c: Support display for Arm64 Joe Mario
@ 2022-06-03 19:33 ` Arnaldo Carvalho de Melo
2022-06-04 1:40 ` Leo Yan
13 siblings, 1 reply; 21+ messages in thread
From: Arnaldo Carvalho de Melo @ 2022-06-03 19:33 UTC (permalink / raw)
To: Leo Yan
Cc: Peter Zijlstra, Ingo Molnar, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Alyssa Ross, Ian Rogers, Like Xu,
Kajol Jain, Li Huafei, Joe Mario, Adam Li, German Gomez,
James Clark, Ali Saidi, linux-perf-users, linux-kernel
Em Mon, May 30, 2022 at 07:40:24PM +0800, Leo Yan escreveu:
> Arm64 Neoverse CPUs supports data source in Arm SPE trace, this allows
> us to detect cache line contention and transfers.
>
> This patch set is based on Ali Said's patch set v9 "perf: arm-spe: Decode SPE
> source and use for perf c2c" [1] and Ali's patch set doesn't need any
> change in this new round.
IIRC there is a kernel part there, please let me know when that part
gets merged so that I can process this 12 patches long set.
- Arnaldo
> To clearly show peer loads and express the local peer loads and remote
> peer lodes, this patch introduces three new metrics 'lcl_peer',
> 'rmt_peer' and 'tot_peer'. The display 'peer' mode uses metric
> 'tot_peer' for sorting cache lines.
>
> Patches 01-05 adds statistics for memory samples, and add dimensions for
> peer metrics.
>
> Patches 06-09 are for refactoring, it refines the code with more general
> naming so this can allow us to easier to extend display modes but not
> strictly bound to HITM tags.
>
> Patches 10-11 are to extend display 'peer' mode, and also changes to use
> 'peer' mode as default mode for Arm64 arches.
>
> Patch 12 updates document to describe the new dimensions for peer
> metrics.
>
> This patch set has been verified for both x86 and Arm64 memory samples.
>
> Known issues: Joe reminded there have an issue in patch set v3 that the
> cache line metric shows 'N/A' for node, this is because Arm SPE trace
> data doesn't contain physical address and leads to perf c2c tool fails
> to find matched node range if physical address is zero. This issue is
> addressed in a separte patch [2]. Since I am still using the old
> perf data file (I have no Neoverse platforms), the output result still
> shows the Node field is 'N/A'.
>
> Another thing is we need to enhance data source setting for old Arm
> platforms. As discussed, German would follow up this task later.
>
> The latest patch set has been uploaded on the git server [3].
>
> The display result with x86 memory samples:
>
> =================================================
> Shared Data Cache Line Table
> =================================================
> #
> # ----------- Cacheline ---------- Tot ------- Load Hitm ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ----
> # Index Address Node PA cnt Hitm Total LclHitm RmtHitm records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt
> # ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........
> #
> 0 0x55c8971f0080 0 1967 66.14% 252 252 0 6044 3550 2494 2024 470 0 528 2672 78 20 252 0 0 0 0
> 1 0x55c8971f00c0 0 1 33.86% 129 129 0 914 914 0 0 0 0 272 374 52 87 129 0 0 0 0
>
> =================================================
> Shared Cache Line Distribution Pareto
> =================================================
> #
> # ----- HITM ----- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared
> # Num RmtHitm LclHitm L1 Hit L1 Miss N/A Offset Node PA cnt Code address rmt hitm lcl hitm load records cnt Symbol Object Source:Line Node
> # ..... ....... ....... ....... ....... ....... .................. .... ...... .................. ........ ........ ........ ....... ........ ...................... ................. ....................... ....
> #
> ----------------------------------------------------------------------
> 0 0 252 2024 470 0 0x55c8971f0080
> ----------------------------------------------------------------------
> 0.00% 12.30% 0.00% 0.00% 0.00% 0x0 0 1 0x55c8971ed3e9 0 1313 863 1222 3 [.] 0x00000000000013e9 false_sharing.exe false_sharing.exe[13e9] 0
> 0.00% 0.79% 90.51% 0.00% 0.00% 0x0 0 1 0x55c8971ed3e2 0 1800 878 3029 3 [.] 0x00000000000013e2 false_sharing.exe false_sharing.exe[13e2] 0
> 0.00% 0.00% 9.49% 100.00% 0.00% 0x0 0 1 0x55c8971ed3f4 0 0 0 662 3 [.] 0x00000000000013f4 false_sharing.exe false_sharing.exe[13f4] 0
> 0.00% 86.90% 0.00% 0.00% 0.00% 0x20 0 1 0x55c8971ed447 0 141 103 1131 2 [.] 0x0000000000001447 false_sharing.exe false_sharing.exe[1447] 0
>
> ----------------------------------------------------------------------
> 1 0 129 0 0 0 0x55c8971f00c0
> ----------------------------------------------------------------------
> 0.00% 100.00% 0.00% 0.00% 0.00% 0x20 0 1 0x55c8971ed455 0 88 94 914 2 [.] 0x0000000000001455 false_sharing.exe false_sharing.exe[1455] 0
>
>
> The display result with Arm SPE:
>
> =================================================
> Shared Data Cache Line Table
> =================================================
> #
> # ----------- Cacheline ---------- Peer ------- Load Peer ------- Total Total Total --------- Stores -------- ----- Core Load Hit ----- - LLC Load Hit -- - RMT Load Hit -- --- Load Dram ----
> # Index Address Node PA cnt Snoop Total Local Remote records Loads Stores L1Hit L1Miss N/A FB L1 L2 LclHit LclHitm RmtHit RmtHitm Lcl Rmt
> # ..... .................. .... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ........ ....... ........ ....... ........ ........
> #
> 0 0xaaaac17d6000 N/A 0 100.00% 99 99 0 18851 18851 0 0 0 0 0 18752 0 99 0 0 0 0 0
>
> =================================================
> Shared Cache Line Distribution Pareto
> =================================================
> #
> # -- Peer Snoop -- ------- Store Refs ------ --------- Data address --------- ---------- cycles ---------- Total cpu Shared
> # Num Rmt Lcl L1 Hit L1 Miss N/A Offset Node PA cnt Code address rmt peer lcl peer load records cnt Symbol Object Source:Line Node{cpus %peers %stores}
> # ..... ....... ....... ....... ....... ....... .................. .... ...... .................. ........ ........ ........ ....... ........ ...................... ................ ............... ....
> #
> ----------------------------------------------------------------------
> 0 0 99 0 0 0 0xaaaac17d6000
> ----------------------------------------------------------------------
> 0.00% 6.06% 0.00% 0.00% 0.00% 0x20 N/A 0 0xaaaac17c25ac 0 375 43 18469 2 [.] 0x00000000000025ac memstress memstress[25ac] 0{ 2 100.0% n/a}
> 0.00% 93.94% 0.00% 0.00% 0.00% 0x29 N/A 0 0xaaaac17c3e88 0 180 173 135 2 [.] 0x0000000000003e88 memstress memstress[3e88] 0{ 2 100.0% n/a}
>
>
> Changes from v3:
> * Changed to display remote and local peer accesses (Joe);
> * Fixed the usage info for display types (Joe);
> * Do not display HITM dimensions when use 'peer' display, and HITM
> display doesn't show any 'peer' dimensions (James);
> * Split to smaller patches for adding dimensions of peer operations;
> * Updated documentation to reflect the latest GUI and stdio.
>
> Changes from v2:
> * Updated patch 04 to account metrics for both cache level and ld_peer
> for PEER flag;
> * Updated document for metric 'rmt_hit' which is accounted for all
> remote accesses (include remote DRAM and any upward caches).
>
> Changes from v1:
> * Updated patches 01, 02 and 03 to support 'N/A' metrics for store
> operations, so can align with the patch set [1] for store samples.
>
>
> [1] https://lore.kernel.org/lkml/20220517020326.18580-1-alisaidi@amazon.com/
> [2] https://lore.kernel.org/lkml/20220530083645.253432-1-leo.yan@linaro.org/
> [3] https://git.linaro.org/people/leo.yan/linux-spe.git/ branch: perf_c2c_arm_spe_peer_v4
>
>
> Leo Yan (12):
> perf mem: Add statistics for peer snooping
> perf c2c: Output statistics for peer snooping
> perf c2c: Add dimensions for peer load operations
> perf c2c: Add dimensions of peer metrics for cache line view
> perf c2c: Add mean dimensions for peer operations
> perf c2c: Use explicit names for display macros
> perf c2c: Rename dimension from 'percent_hitm' to
> 'percent_costly_snoop'
> perf c2c: Refactor node header
> perf c2c: Refactor display string
> perf c2c: Sort on peer snooping for load operations
> perf c2c: Use 'peer' as default display for Arm64
> perf c2c: Update documentation for new display option 'peer'
>
> tools/perf/Documentation/perf-c2c.txt | 30 +-
> tools/perf/builtin-c2c.c | 454 ++++++++++++++++++++------
> tools/perf/util/mem-events.c | 28 +-
> tools/perf/util/mem-events.h | 3 +
> 4 files changed, 403 insertions(+), 112 deletions(-)
>
> --
> 2.25.1
--
- Arnaldo
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 00/12] perf c2c: Support display for Arm64
2022-06-03 19:33 ` Arnaldo Carvalho de Melo
@ 2022-06-04 1:40 ` Leo Yan
0 siblings, 0 replies; 21+ messages in thread
From: Leo Yan @ 2022-06-04 1:40 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: Peter Zijlstra, Ingo Molnar, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Alyssa Ross, Ian Rogers, Like Xu,
Kajol Jain, Li Huafei, Joe Mario, Adam Li, German Gomez,
James Clark, Ali Saidi, linux-perf-users, linux-kernel
Hi Arnaldo,
On Fri, Jun 03, 2022 at 09:33:10PM +0200, Arnaldo Carvalho de Melo wrote:
> Em Mon, May 30, 2022 at 07:40:24PM +0800, Leo Yan escreveu:
> > Arm64 Neoverse CPUs supports data source in Arm SPE trace, this allows
> > us to detect cache line contention and transfers.
> >
> > This patch set is based on Ali Said's patch set v9 "perf: arm-spe: Decode SPE
> > source and use for perf c2c" [1] and Ali's patch set doesn't need any
> > change in this new round.
>
> IIRC there is a kernel part there, please let me know when that part
> gets merged so that I can process this 12 patches long set.
This patch set is not dependent on any kernel patch, it bases on Ali's
patch set "perf: arm-spe: Decode SPE source and use for perf c2c".
Let me use a new patch set to include all relevant patches (include
Ali's patches for setting data source and this patch set), will send
out soon. Hope this would be easier for picking up.
Thanks,
Leo
P.s. James' patch set for enabling SVE register is dependent on kernel
changes, James is on vacation, I will monitor the latest status and
update in the corresponding patch set thread.
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2022-06-04 1:40 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-30 11:40 [PATCH v4 00/12] perf c2c: Support display for Arm64 Leo Yan
2022-05-30 11:40 ` [PATCH v4 01/12] perf mem: Add statistics for peer snooping Leo Yan
2022-05-30 11:40 ` [PATCH v4 02/12] perf c2c: Output " Leo Yan
2022-05-30 11:40 ` [PATCH v4 03/12] perf c2c: Add dimensions for peer load operations Leo Yan
2022-05-30 11:40 ` [PATCH v4 04/12] perf c2c: Add dimensions of peer metrics for cache line view Leo Yan
2022-05-30 11:40 ` [PATCH v4 05/12] perf c2c: Add mean dimensions for peer operations Leo Yan
2022-05-30 11:40 ` [PATCH v4 06/12] perf c2c: Use explicit names for display macros Leo Yan
2022-05-30 11:40 ` [PATCH v4 07/12] perf c2c: Rename dimension from 'percent_hitm' to 'percent_costly_snoop' Leo Yan
2022-05-30 11:40 ` [PATCH v4 08/12] perf c2c: Refactor node header Leo Yan
2022-05-30 11:40 ` [PATCH v4 09/12] perf c2c: Refactor display string Leo Yan
2022-05-30 11:40 ` [PATCH v4 10/12] perf c2c: Sort on peer snooping for load operations Leo Yan
2022-05-30 11:40 ` [PATCH v4 11/12] perf c2c: Use 'peer' as default display for Arm64 Leo Yan
2022-05-30 11:40 ` [PATCH v4 12/12] perf c2c: Update documentation for new display option 'peer' Leo Yan
2022-05-31 18:44 ` [PATCH v4 00/12] perf c2c: Support display for Arm64 Joe Mario
2022-06-01 10:25 ` Leo Yan
2022-06-02 16:59 ` Ian Rogers
2022-06-03 3:36 ` Leo Yan
2022-06-02 17:11 ` Ali Saidi
2022-06-03 3:46 ` Leo Yan
2022-06-03 19:33 ` Arnaldo Carvalho de Melo
2022-06-04 1:40 ` Leo Yan
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