From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2537C433F5 for ; Wed, 29 Sep 2021 16:51:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9731D61440 for ; Wed, 29 Sep 2021 16:51:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245643AbhI2QxE convert rfc822-to-8bit (ORCPT ); Wed, 29 Sep 2021 12:53:04 -0400 Received: from mga18.intel.com ([134.134.136.126]:13848 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243893AbhI2QxD (ORCPT ); Wed, 29 Sep 2021 12:53:03 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10122"; a="212071487" X-IronPort-AV: E=Sophos;i="5.85,332,1624345200"; d="scan'208";a="212071487" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2021 09:51:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,332,1624345200"; d="scan'208";a="476702306" Received: from fmsmsx604.amr.corp.intel.com ([10.18.126.84]) by orsmga007.jf.intel.com with ESMTP; 29 Sep 2021 09:51:18 -0700 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Wed, 29 Sep 2021 09:51:17 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx612.amr.corp.intel.com (10.18.126.92) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Wed, 29 Sep 2021 09:51:15 -0700 Received: from fmsmsx610.amr.corp.intel.com ([10.18.126.90]) by fmsmsx610.amr.corp.intel.com ([10.18.126.90]) with mapi id 15.01.2242.012; Wed, 29 Sep 2021 09:51:15 -0700 From: "Luck, Tony" To: Thomas Gleixner , Peter Zijlstra , Andy Lutomirski CC: "Yu, Fenghua" , Ingo Molnar , Borislav Petkov , "Hansen, Dave" , "Lu Baolu" , Joerg Roedel , "Josh Poimboeuf" , "Jiang, Dave" , "Pan, Jacob jun" , "Raj, Ashok" , "Shankar, Ravi V" , "iommu@lists.linux-foundation.org" , "the arch/x86 maintainers" , Linux Kernel Mailing List Subject: RE: [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting Thread-Topic: [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting Thread-Index: AQHXrlppKq1JNDzwUU2jIMumR+OY2auyKYcA//+tUICAAIgmgIABRuYA//+7QwCAAOhhgIAG/wKAgAArB4D//9OUcA== Date: Wed, 29 Sep 2021 16:51:15 +0000 Message-ID: <57d0e4efcf2d4e9abb91801520a3f386@intel.com> References: <20210920192349.2602141-1-fenghua.yu@intel.com> <20210920192349.2602141-6-fenghua.yu@intel.com> <87y27nfjel.ffs@tglx> <87o88jfajo.ffs@tglx> <87k0j6dsdn.ffs@tglx> <87r1d78t2e.ffs@tglx> In-Reply-To: <87r1d78t2e.ffs@tglx> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.200.16 x-originating-ip: [10.1.200.100] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > There is zero requirement to look at TIF_NEED_FPU_LOAD or > fpregs_state_valid() simply because the #GP comes straight from user > space which means the FPU registers contain the current tasks user space > state. Just to double confirm ... there is no point in the #GP handler up to this point where pre-emption can occur? -Tony