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[72.225.192.120]) by smtp.gmail.com with ESMTPSA id m15-20020a05620a13af00b006cfc1d827cbsm15705502qki.9.2022.10.12.08.38.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Oct 2022 08:38:33 -0700 (PDT) Message-ID: <57e454f4-6767-bf42-8337-ce1f486137ca@linaro.org> Date: Wed, 12 Oct 2022 11:38:17 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [RFC PATCH 0/2] RZ/G2UL separate out SoC specific parts Content-Language: en-US To: "Lad, Prabhakar" , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski Cc: Conor Dooley , Samuel Holland , linux-riscv , Linux ARM , Linux-Renesas , DT , LKML , Biju Das , Lad Prabhakar References: <20220929172356.301342-1-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/10/2022 05:41, Lad, Prabhakar wrote: > Hi Rob, Krzysztof, > > On Thu, Sep 29, 2022 at 6:24 PM Prabhakar wrote: >> >> From: Lad Prabhakar >> >> Hi All, >> >> This patch series aims to split up the RZ/G2UL SoC DTSI into common parts >> so that this can be shared with the RZ/Five SoC. >> >> Implementation is based on the discussion [0] where I have used option#2. >> >> The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same >> identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is >> created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five >> (r9a07g043F.dtsi) >> >> Sending this as an RFC to get some feedback. >> >> r9a07g043f.dtsi will look something like below: >> >> #include >> >> #define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32) >> #define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na >> >> #include >> >> / { >> ... >> ... >> }; >> >> Although patch#2 can be merged into patch#1 just wanted to keep them separated >> for easier review. >> >> [0] https://lore.kernel.org/linux-arm-kernel/Yyt8s5+pyoysVNeC@spud/T/ >> >> Cheers, >> Prabhakar >> >> Lad Prabhakar (2): >> arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro >> to specify interrupt property > > Can either of you please review patch #1. > Why? This is a DTS patch, isn't it? You should CC rather platform maintainers, architecture maintainers and SoC folks (the latter you missed for sure). You missed them, so please resend. Best regards, Krzysztof