From: Xunlei Pang <xpang@redhat.com>
To: Borislav Petkov <bp@alien8.de>, xlpang@redhat.com
Cc: Prarit Bhargava <prarit@redhat.com>,
Kiyoshi Ueda <k-ueda@ct.jp.nec.com>,
Tony Luck <tony.luck@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
x86@kernel.org, kexec@lists.infradead.org,
linux-kernel@vger.kernel.org, Ingo Molnar <mingo@redhat.com>,
Junichi Nomura <j-nomura@ce.jp.nec.com>,
Naoya Horiguchi <n-horiguchi@ah.jp.nec.com>,
Dave Young <dyoung@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH] x86/mce: Keep quiet in case of broadcasted mce after system panic
Date: Sat, 18 Feb 2017 00:21:42 +0800 [thread overview]
Message-ID: <58A72316.20204@redhat.com> (raw)
In-Reply-To: <20170217090735.ls5pmtsfwkf3q5h6@pd.tnic>
On 02/17/2017 at 05:07 PM, Borislav Petkov wrote:
> On Fri, Feb 17, 2017 at 09:53:21AM +0800, Xunlei Pang wrote:
>> It changes the value of cpu_online_mask/etc which will cause confusion to vmcore analysis.
> Then export the crashing_cpu variable, initialize it to something
> invalid in the first kernel, -1 for example, and test it in the #MC
> handlier like this:
>
> int cpu;
>
> ...
>
> cpu = smp_processor_id();
>
> if (cpu_is_offline(cpu) ||
> ((crashing_cpu != -1) && (crashing_cpu != cpu)) {
> u64 mcgstatus;
>
> mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
> if (mcgstatus & MCG_STATUS_RIPV) {
> mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
> return;
> }
> }
Yes, it is doable, I will do some tests later.
>> Moreover, for the code(see comment inlined)
>>
>> if (cpu_is_offline(smp_processor_id())) {
>> u64 mcgstatus;
>>
>> mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
>> if (mcgstatus & MCG_STATUS_RIPV) { // This condition may be not true, the mce triggered on kdump cpu
>> // doesn't need to have this bit set for the other cpus remain in 1st kernel.
> Is this on kvm or on a real hardware? Because for kvm I don't care. And
> don't say "theoretically".
>
It's from my understanding, I didn't get the explicit description from the intel SDM on this point.
If a broadcast SRAO comes on real hardware, will MSR_IA32_MCG_STATUS of each cpu have MCG_STATUS_RIPV bit set?
Regards,
Xunlei
next prev parent reply other threads:[~2017-02-17 16:19 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-23 8:01 [PATCH] x86/mce: Keep quiet in case of broadcasted mce after system panic Xunlei Pang
2017-01-23 12:51 ` Borislav Petkov
2017-01-23 13:35 ` Xunlei Pang
2017-01-23 14:50 ` Borislav Petkov
2017-01-23 17:40 ` Luck, Tony
2017-01-23 17:51 ` Borislav Petkov
2017-01-23 18:01 ` Luck, Tony
2017-01-23 18:14 ` Borislav Petkov
2017-01-24 2:33 ` Xunlei Pang
2017-01-24 1:46 ` Xunlei Pang
2017-01-24 1:51 ` Xunlei Pang
2017-01-24 1:27 ` Xunlei Pang
2017-01-24 12:22 ` Borislav Petkov
2017-01-26 6:30 ` Xunlei Pang
2017-01-26 6:44 ` Borislav Petkov
2017-02-16 5:36 ` Xunlei Pang
2017-02-16 10:18 ` Borislav Petkov
2017-02-16 11:52 ` Xunlei Pang
2017-02-16 12:22 ` Borislav Petkov
2017-02-17 1:53 ` Xunlei Pang
2017-02-17 9:07 ` Borislav Petkov
2017-02-17 16:21 ` Xunlei Pang [this message]
2017-02-21 18:20 ` Luck, Tony
2017-02-22 5:50 ` Xunlei Pang
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