From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937012AbdCJNF4 (ORCPT ); Fri, 10 Mar 2017 08:05:56 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:20686 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933801AbdCJNFt (ORCPT ); Fri, 10 Mar 2017 08:05:49 -0500 Subject: Re: [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes To: Niklas Cassel , Bjorn Helgaas , Joao Pinto , , , , References: <1489041545-15730-1-git-send-email-kishon@ti.com> <1489041545-15730-6-git-send-email-kishon@ti.com> <58C29648.5020708@ti.com> <61f90a03-7164-8e79-f1c2-0ae48b5892a8@axis.com> CC: , Jingoo Han , Richard Zhu , Lucas Stach , Murali Karicheri , Thomas Petazzoni , Jesper Nilsson , Zhou Wang , Gabriele Paoloni From: Kishon Vijay Abraham I Message-ID: <58C2A46D.2080907@ti.com> Date: Fri, 10 Mar 2017 18:34:45 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <61f90a03-7164-8e79-f1c2-0ae48b5892a8@axis.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Friday 10 March 2017 06:26 PM, Niklas Cassel wrote: > On 03/10/2017 01:04 PM, Kishon Vijay Abraham I wrote: >> Hi, >> >> On Thursday 09 March 2017 08:18 PM, Niklas Cassel wrote: >>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote: >>>> Previously dbi accessors can be used to access data of size 4 >>>> bytes. But there might be situations (like accessing >>>> MSI_MESSAGE_CONTROL in order to set/get the number of required >>>> MSI interrupts in EP mode) where dbi accessors must >>>> be used to access data of size 2. This is in preparation for >>>> adding endpoint mode support to designware driver. >>> Hello Kishon >>> >>> I don't really like the idea of adding an extra argument to every existing read/write. >>> Will not a read/write of length != 32 be quite uncommon compared to >>> a read/write of length == 32? >>> >>> How about adding some defines to pcie-designware.h: >>> >>> #define dw_pcie_writel_dbi(pci, base, reg, val) dw_pcie_write_dbi(pci, base, reg, 0x4, val) >>> #define dw_pcie_readl_dbi(pci, base, reg) dw_pcie_read_dbi(pci, base, reg, 0x4) >>> >>> That way we don't have to change every existing read/write. >>> >>> >>> >>> Is there a reason why we can't just do: >>> >>> vial = dw_pcie_readl_dbi(pci, base, MSI_MESSAGE_CONTROL); >> MSI_MESSAGE_CONTROL is 0x52 (MSI capability offset + 2). I'm not sure if we can >> do a readl that crosses the alignment boundary in all platforms. The other >> option is to readl from "MSI capability offset + 0" and extract the last 16 >> bits. I felt this is more clear since we are interested only in the >> MSI_MESSAGE_CONTROL. >> >>> >>> dw_pcie_writel_dbi(pci, base, MSI_MESSAGE_CONTROL, val); >>> >>> Or are we going to be doing read/writes of length != 32 so often that >>> you think that it's cleaner to have this abstraction? >> it's used mainly for accessing configuration space header fields. Even the pci >> core uses *pci_read_config_word* for accessing such fields. > > I see. Adding an extra size argument is a good thing then, > since it's consistent with the pci generic code. > > However, I still think that having defines for writel/readl is a > good thing :) sure, having defines is fine. How about something like below (readl, readw: to differentiate 4byte and 2 byte access?) #define dw_pcie_readl_dbi(pci, base, reg) __dw_pcie_read_dbi(pci, base, reg, 0x4) #define dw_pcie_readw_dbi(pci, base, reg) __dw_pcie_read_dbi(pci, base, reg, 0x2) Thanks Kishon