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([2600:1010:b062:827f:f4a7:a1e:b790:5671]) by smtp.gmail.com with ESMTPSA id r33sm806663pjb.5.2019.11.21.18.13.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Nov 2019 18:13:19 -0800 (PST) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Andy Lutomirski Mime-Version: 1.0 (1.0) Subject: Re: [PATCH v10 4/6] x86/split_lock: Enumerate split lock detection if the IA32_CORE_CAPABILITIES MSR is not supported Date: Thu, 21 Nov 2019 18:13:18 -0800 Message-Id: <5A85615E-EFFF-4DF3-A1A5-DB8532451A42@amacapital.net> References: <20191122003754.GF199273@romley-ivt3.sc.intel.com> Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , H Peter Anvin , Peter Zijlstra , Tony Luck , Ashok Raj , Ravi V Shankar , linux-kernel , x86 In-Reply-To: <20191122003754.GF199273@romley-ivt3.sc.intel.com> To: Fenghua Yu X-Mailer: iPhone Mail (17A878) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Nov 21, 2019, at 4:25 PM, Fenghua Yu wrote: >=20 > =EF=BB=BFOn Thu, Nov 21, 2019 at 02:07:38PM -0800, Andy Lutomirski wrote: >>=20 >>=20 >>>> On Nov 20, 2019, at 5:45 PM, Fenghua Yu wrote: >>>=20 >>> =EF=BB=BFArchitecturally the split lock detection feature is enumerated b= y >>> IA32_CORE_CAPABILITIES MSR and future CPU models will indicate presence >>> of the feature by setting bit 5. But the feature is present in a few >>> older models where split lock detection is enumerated by the CPU models.= >>>=20 >>> Use a "x86_cpu_id" table to list the older CPU models with the feature. >>>=20 >>=20 >> This may need to be disabled if the HYPERVISOR bit is set. >=20 > How about just keeping this patch set as basic enabling code and > keep HYPERVISOR out of scope as of now? KVM folks will have better > handling of split lock in KVM once this patch set is available in > the kernel. >=20 >=20 You seem to be assuming that certain model CPUs have this feature even if no= t enumerated. You need to make sure you don=E2=80=99t try to use it in a VM w= ithout the hypervisor giving you an indication that it=E2=80=99s available a= nd permitted. My suggestion is to disable model-based enumeration if HYPERVI= SOR is set. You should also consider probing the MSR to double check even i= f you don=E2=80=99t think you have a hypervisor.=