From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECCF8C43444 for ; Thu, 10 Jan 2019 06:30:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BCE2F206B7 for ; Thu, 10 Jan 2019 06:30:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727431AbfAJGak (ORCPT ); Thu, 10 Jan 2019 01:30:40 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:39946 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725536AbfAJGaj (ORCPT ); Thu, 10 Jan 2019 01:30:39 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 2F52B1087376447647FC; Thu, 10 Jan 2019 14:30:37 +0800 (CST) Received: from [127.0.0.1] (10.63.139.185) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.408.0; Thu, 10 Jan 2019 14:30:27 +0800 Subject: Re: [PATCH 0/4] crypto: hisilicon: Add HiSilicon QM and ZIP controller driver To: Herbert Xu , "David S . Miller" , References: <1545465105-133138-1-git-send-email-wangzhou1@hisilicon.com> CC: , From: Zhou Wang Message-ID: <5C36E682.9040701@hisilicon.com> Date: Thu, 10 Jan 2019 14:30:26 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1545465105-133138-1-git-send-email-wangzhou1@hisilicon.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.63.139.185] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2018/12/22 15:51, Zhou Wang wrote: > This series adds HiSilicon QM and ZIP controller driver in crypto subsystem. > > A simple QM/ZIP driver which helps to provide an example for a general > accelerator framework is under review in community[1]. Based on this simple > driver, this series adds HW v2 support, PCI passthrough, reset, PCI/misc error > handler, debug support. But unlike [1], driver in this patchset only registers > to crypto subsystem. > > There will be a long discussion about above accelerator framework in the > process of upstreaming. So let's firstly review and upstream QM/ZIP crypto > driver. > > References: > [1] https://lkml.org/lkml/2018/11/12/1951 > > Zhou Wang (4): > Documentation: Add debugfs doc for hisi_zip > crypto: hisilicon: Add queue management driver for HiSilicon QM module > crypto: hisilicon: Add HiSilicon ZIP accelerator support > MAINTAINERS: add maintainer for HiSilicon QM and ZIP controller driver > > Documentation/ABI/testing/debugfs-hisi-zip | 50 + > MAINTAINERS | 8 + > drivers/crypto/hisilicon/Kconfig | 11 + > drivers/crypto/hisilicon/Makefile | 2 + > drivers/crypto/hisilicon/qm.c | 1823 ++++++++++++++++++++++++++++ > drivers/crypto/hisilicon/qm.h | 177 +++ > drivers/crypto/hisilicon/zip/Makefile | 2 + > drivers/crypto/hisilicon/zip/zip.h | 60 + > drivers/crypto/hisilicon/zip/zip_crypto.c | 410 +++++++ > drivers/crypto/hisilicon/zip/zip_main.c | 1161 ++++++++++++++++++ > 10 files changed, 3704 insertions(+) > create mode 100644 Documentation/ABI/testing/debugfs-hisi-zip > create mode 100644 drivers/crypto/hisilicon/qm.c > create mode 100644 drivers/crypto/hisilicon/qm.h > create mode 100644 drivers/crypto/hisilicon/zip/Makefile > create mode 100644 drivers/crypto/hisilicon/zip/zip.h > create mode 100644 drivers/crypto/hisilicon/zip/zip_crypto.c > create mode 100644 drivers/crypto/hisilicon/zip/zip_main.c > Any comments about this series? Best, Zhou