From: Wei Wang <wei.w.wang@intel.com>
To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
ak@linux.intel.com, peterz@infradead.org, pbonzini@redhat.com
Cc: kan.liang@intel.com, mingo@redhat.com, rkrcmar@redhat.com,
like.xu@intel.com, jannh@google.com, arei.gonglei@huawei.com,
jmattson@google.com
Subject: Re: [PATCH v8 13/14] KVM/x86/vPMU: check the lbr feature before entering guest
Date: Wed, 07 Aug 2019 14:02:37 +0800 [thread overview]
Message-ID: <5D4A697D.3030604@intel.com> (raw)
In-Reply-To: <1565075774-26671-14-git-send-email-wei.w.wang@intel.com>
On 08/06/2019 03:16 PM, Wei Wang wrote:
> The guest can access the lbr related msrs only when the vcpu's lbr event
> has been assigned the lbr feature. A cpu pinned lbr event (though no such
> event usages in the current upstream kernel) could reclaim the lbr feature
> from the vcpu's lbr event (task pinned) via ipi calls. If the cpu is
> running in the non-root mode, this will cause the cpu to vm-exit to handle
> the host ipi and then vm-entry back to the guest. So on vm-entry (where
> interrupt has been disabled), we double confirm that the vcpu's lbr event
> is still assigned the lbr feature via checking event->oncpu.
>
> The pass-through of the lbr related msrs will be cancelled if the lbr is
> reclaimed, and the following guest accesses to the lbr related msrs will
> vm-exit to the related msr emulation handler in kvm, which will prevent
> the accesses.
>
> Signed-off-by: Wei Wang <wei.w.wang@intel.com>
> ---
> arch/x86/kvm/pmu.c | 6 ++++++
> arch/x86/kvm/pmu.h | 3 +++
> arch/x86/kvm/vmx/pmu_intel.c | 35 +++++++++++++++++++++++++++++++++++
> arch/x86/kvm/x86.c | 13 +++++++++++++
> 4 files changed, 57 insertions(+)
>
> diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
> index afad092..ed10a57 100644
> --- a/arch/x86/kvm/pmu.c
> +++ b/arch/x86/kvm/pmu.c
> @@ -339,6 +339,12 @@ bool kvm_pmu_lbr_enable(struct kvm_vcpu *vcpu)
> return false;
> }
>
> +void kvm_pmu_enabled_feature_confirm(struct kvm_vcpu *vcpu)
> +{
> + if (kvm_x86_ops->pmu_ops->enabled_feature_confirm)
> + kvm_x86_ops->pmu_ops->enabled_feature_confirm(vcpu);
> +}
> +
> void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
> {
> if (lapic_in_kernel(vcpu))
> diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h
> index f875721..7467907 100644
> --- a/arch/x86/kvm/pmu.h
> +++ b/arch/x86/kvm/pmu.h
> @@ -30,6 +30,7 @@ struct kvm_pmu_ops {
> int (*is_valid_msr_idx)(struct kvm_vcpu *vcpu, unsigned idx);
> bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr);
> bool (*lbr_enable)(struct kvm_vcpu *vcpu);
> + void (*enabled_feature_confirm)(struct kvm_vcpu *vcpu);
> int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
> int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
> void (*sched_in)(struct kvm_vcpu *vcpu, int cpu);
> @@ -126,6 +127,8 @@ int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp);
>
> bool is_vmware_backdoor_pmc(u32 pmc_idx);
>
> +void kvm_pmu_enabled_feature_confirm(struct kvm_vcpu *vcpu);
> +
> extern struct kvm_pmu_ops intel_pmu_ops;
> extern struct kvm_pmu_ops amd_pmu_ops;
> #endif /* __KVM_X86_PMU_H */
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index 5580f1a..421051aa 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -781,6 +781,40 @@ static void intel_pmu_reset(struct kvm_vcpu *vcpu)
> intel_pmu_free_lbr_event(vcpu);
> }
>
> +void intel_pmu_lbr_confirm(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
> +
> + /*
> + * Either lbr_event being NULL or lbr_used being false indicates that
> + * the lbr msrs haven't been passed through to the guest, so no need
> + * to cancel passthrough.
> + */
> + if (!pmu->lbr_event || !pmu->lbr_used)
> + return;
> +
> + /*
> + * The lbr feature gets reclaimed via IPI calls, so checking of
> + * lbr_event->oncpu needs to be in an atomic context. Just confirm
> + * that irq has been disabled already.
> + */
> + lockdep_assert_irqs_disabled();
> +
> + /*
> + * Cancel the pass-through of the lbr msrs if lbr has been reclaimed
> + * by the host perf.
> + */
> + if (pmu->lbr_event->oncpu != -1) {
A mistake here, should be "pmu->lbr_event->oncpu == -1".
(It didn't seem to affect the profiling result, but generated
more vm-exits due to mistakenly cancelling the passthrough)
Best,
Wei
next prev parent reply other threads:[~2019-08-07 5:56 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-06 7:16 [PATCH v8 00/14] Guest LBR Enabling Wei Wang
2019-08-06 7:16 ` [PATCH v8 01/14] perf/x86: fix the variable type of the lbr msrs Wei Wang
2019-08-06 7:16 ` [PATCH v8 02/14] perf/x86: add a function to get the addresses of the lbr stack msrs Wei Wang
2019-08-06 7:16 ` [PATCH v8 03/14] KVM/x86: KVM_CAP_X86_GUEST_LBR Wei Wang
2019-08-06 7:16 ` [PATCH v8 04/14] KVM/x86: intel_pmu_lbr_enable Wei Wang
2019-08-06 7:16 ` [PATCH v8 05/14] KVM/x86/vPMU: tweak kvm_pmu_get_msr Wei Wang
2019-08-06 7:16 ` [PATCH v8 06/14] KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest Wei Wang
2019-08-06 7:16 ` [PATCH v8 07/14] perf/x86: support to create a perf event without counter allocation Wei Wang
2019-08-06 7:16 ` [PATCH v8 08/14] perf/core: set the event->owner before event_init Wei Wang
2019-08-06 7:16 ` [PATCH v8 09/14] KVM/x86/vPMU: APIs to create/free lbr perf event for a vcpu thread Wei Wang
2019-08-06 7:16 ` [PATCH v8 10/14] perf/x86/lbr: don't share lbr for the vcpu usage case Wei Wang
2019-08-06 7:16 ` [PATCH v8 11/14] perf/x86: save/restore LBR_SELECT on vcpu switching Wei Wang
2019-08-06 7:16 ` [PATCH v8 12/14] KVM/x86/lbr: lbr emulation Wei Wang
2019-12-10 23:37 ` Sean Christopherson
2019-08-06 7:16 ` [PATCH v8 13/14] KVM/x86/vPMU: check the lbr feature before entering guest Wei Wang
2019-08-07 6:02 ` Wei Wang [this message]
2019-08-06 7:16 ` [PATCH v8 14/14] KVM/x86: remove the common handling of the debugctl msr Wei Wang
2019-09-06 8:50 ` [PATCH v8 00/14] Guest LBR Enabling Wang, Wei W
2020-01-30 20:14 ` Eduardo Habkost
2020-01-31 1:01 ` Wang, Wei W
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