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From: Atish Patra <>
To: Paul Walmsley <>
Cc: "" <>,
	Albert Ou <>,
	Alexios Zavras <>,
	Allison Randal <>,
	Anup Patel <>,
	Daniel Lezcano <>,
	"" <>,
	Enrico Weigelt <>,
	Greg Kroah-Hartman <>,
	Johan Hovold <>,
	Mark Rutland <>,
	Palmer Dabbelt <>,
	Rob Herring <>,
	Thomas Gleixner <>
Subject: Re: [PATCH v2 5/5] dt-bindings: Update the isa string description
Date: Wed, 31 Jul 2019 06:43:21 +0000	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

On 7/30/19, 9:52 PM, "Paul Walmsley" <> wrote:

    On Tue, 30 Jul 2019, Atish Patra wrote:
    > The yaml documentation description of isa strings section doesn't
    > specify anything about the case sensitiveness of the isa strings.
    > The RISC-V specification clearly specifies it to be case insensitive.
    > However, Linux kernel supports only lower case isa strings.
    The DT binding documentation specifies an interface.  As such the binding 
    isn't determined by any particular piece of software.  So justifying the 
    binding update by referring to what the Linux kernel currently supports 
    isn't that relevant.  If you still really believe that software should be 
    required to handle mixed-case DT ISA strings, the right answer would be to 
    change the software, as your original patches proposed.  The way you've 
    written this patch description, it sounds like you still don't agree with 
    the conclusion that a strictly lowercase string is a good approach.
    If I've misunderstood your intent here, and you do think that specifying 
    an all lowercase string is sufficient,

I think that specifying an all lowercase string is sufficient. I did not 
realize that current commit text could mean something else (.

 then instead of the patch 
    description above, how about something like:
    "Since the RISC-V specification states that ISA description strings are 
    case-insensitive, there's no functional difference between mixed-case, 
    upper-case, and lower-case ISA strings.  Thus, to simplify parsing, 
    specify that the letters present of riscv,isa must be all lowercase."
Sounds good to me. I will update the patch. Thanks for updated commit text.

    That way it's clear that, per the RISC-V specification, there's no 
    functional difference associated with case.
    However, if what you're saying is that you still don't like this outcome, 
    let me know and I'll write the patch myself.  That way you don't have to 
    have your name associated with a change that you don't believe in.
    > Update the yaml documentation accordingly to avoid any confusion.
    > Signed-off-by: Atish Patra <>
    > ---
    >  Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
    >  1 file changed, 5 insertions(+), 1 deletion(-)
    > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
    > index c899111aa5e3..e22a2b7ebafa 100644
    > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
    > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
    > @@ -46,10 +46,14 @@ properties:
    >            - rv64imafdc
    >      description:
    >        Identifies the specific RISC-V instruction set architecture
    > -      supported by the hart.  These are documented in the RISC-V
    > +      supported by the hart. These are documented in the RISC-V
    >        User-Level ISA document, available from
    > +      Linux kernel only supports lower case isa strings. Thus,
    In the past, the DT maintainers have pushed back against explicitly 
    mentioning the Linux kernel in binding documentation, since the DT 
    bindings define an interface that's independent of the underlying software 
    implementation.  How about just stating something like "Letters in the 
    riscv,isa string must be all lowercase" ?


    > +      isa strings must be specified in lower case in device tree
    > +      as well.
    > +
    - Paul

      reply	other threads:[~2019-07-31  6:43 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-31  1:24 [PATCH v2 0/5] Miscellaneous fixes Atish Patra
2019-07-31  1:24 ` [PATCH v2 1/5] RISC-V: Remove per cpu clocksource Atish Patra
2019-08-16 15:09   ` Daniel Lezcano
2019-08-16 18:55     ` Atish Patra
2019-08-26 23:48       ` Palmer Dabbelt
2019-07-31  1:24 ` [PATCH v2 2/5] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs Atish Patra
2019-07-31  4:23   ` Paul Walmsley
2019-07-31  6:27     ` Atish Patra
2019-07-31  1:24 ` [PATCH v2 3/5] RISC-V: Fix unsupported isa string info Atish Patra
2019-07-31  1:24 ` [PATCH v2 4/5] RISC-V: Export few kernel symbols Atish Patra
2019-07-31  1:24 ` [PATCH v2 5/5] dt-bindings: Update the isa string description Atish Patra
2019-07-31  4:52   ` Paul Walmsley
2019-07-31  6:43     ` Atish Patra [this message]

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