From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Rob Clark <robdclark@gmail.com>, dri-devel@lists.freedesktop.org
Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
Rob Clark <robdclark@chromium.org>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Akhil P Oommen <quic_akhilpo@quicinc.com>,
Chia-I Wu <olvaffe@gmail.com>,
Douglas Anderson <dianders@chromium.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] drm/msm/a6xx: Some reg64 conversion
Date: Mon, 20 Mar 2023 19:57:26 +0100 [thread overview]
Message-ID: <5a9e6cdb-f640-f070-6722-18e61c9f1136@linaro.org> (raw)
In-Reply-To: <434caf75-eed1-ac35-f43c-da8c66cb99bc@somainline.org>
On 20.03.2023 19:56, Konrad Dybcio wrote:
>
>
> On 20.03.2023 19:54, Rob Clark wrote:
>> From: Rob Clark <robdclark@chromium.org>
>>
>> The next generated header update will drop the _LO/_HI suffix, now that
>> the userspace tooling properly understands 64b vs 32b regs (and the _LO/
>> _HI workarounds are getting cleaned up). So convert to using the 64b
>> reg helpers in prep.
>>
>> Signed-off-by: Rob Clark <robdclark@chromium.org>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +++------
>> 1 file changed, 3 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index 89049094a242..f26e258c6021 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -1053,12 +1053,9 @@ static int hw_init(struct msm_gpu *gpu)
>> gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
>>
>> /* Disable L2 bypass in the UCHE */
>> - gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);
>> - gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);
>> - gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);
>> - gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);
>> - gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
>> - gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
>> + gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0x0001ffffffffffc0llu);
>> + gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0x0001fffffffff000llu);
>> + gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0x1fffffffff000llu);
> Any reason the last write dropped the leading zeroes?
>
> Otherwise,
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Bah, thunderfox sent it from the wrong email. It still stands.
Konrad
>
> Konrad
>>
>> if (!adreno_is_a650_family(adreno_gpu)) {
>> /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
next prev parent reply other threads:[~2023-03-20 19:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 18:54 [PATCH 1/2] drm/msm/a6xx: Some reg64 conversion Rob Clark
2023-03-20 18:54 ` [PATCH 2/2] drm/msm: Update generated headers Rob Clark
2023-03-20 18:56 ` [PATCH 1/2] drm/msm/a6xx: Some reg64 conversion Konrad Dybcio
2023-03-20 18:57 ` Konrad Dybcio [this message]
2023-03-20 20:32 ` Rob Clark
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