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[92.95.37.77]) by smtp.googlemail.com with ESMTPSA id b12sm2861827wrt.17.2018.12.14.01.17.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Dec 2018 01:17:26 -0800 (PST) Subject: Re: [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency To: Atish Patra , linux-kernel@vger.kernel.org Cc: Palmer Dabbelt , Christoph Hellwig , Albert Ou , devicetree@vger.kernel.org, Dmitriy Cherkasov , linux-riscv@lists.infradead.org, Mark Rutland , Rob Herring , Thomas Gleixner , Anup Patel , Damien Le Moal , Christoph Hellwig References: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> <1544742869-19980-2-git-send-email-atish.patra@wdc.com> From: Daniel Lezcano Message-ID: <5d652370-4782-23b2-9896-b9666b3cc1e7@linaro.org> Date: Fri, 14 Dec 2018 10:17:24 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <1544742869-19980-2-git-send-email-atish.patra@wdc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/12/2018 00:14, Atish Patra wrote: > From: Palmer Dabbelt > > In RISC-V systems, timebase-frequency is per cpu instead of one > instance for entire SOC as there is a individual timer per each CPU. > Fix the DT binding accordingly. Why not use a fixed-clock instead of this timebase property which forces to declare a global variable to be exported from arch/riscv to drivers/clocksource ? In addition, please add the 'Fixes' tag > Signed-off-by: Palmer Dabbelt > Signed-off-by: Christoph Hellwig > [Atish: Update the commit text] > Signed-off-by: Atish Patra > Reviewed-by: Rob Herring > --- > Documentation/devicetree/bindings/riscv/cpus.txt | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt > index adf7b7af..b0b038d6 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.txt > +++ b/Documentation/devicetree/bindings/riscv/cpus.txt > @@ -93,9 +93,9 @@ Linux is allowed to run on. > cpus { > #address-cells = <1>; > #size-cells = <0>; > - timebase-frequency = <1000000>; > cpu@0 { > clock-frequency = <1600000000>; > + timebase-frequency = <1000000>; > compatible = "sifive,rocket0", "riscv"; > device_type = "cpu"; > i-cache-block-size = <64>; > @@ -113,6 +113,7 @@ Linux is allowed to run on. > }; > cpu@1 { > clock-frequency = <1600000000>; > + timebase-frequency = <1000000>; > compatible = "sifive,rocket0", "riscv"; > d-cache-block-size = <64>; > d-cache-sets = <64>; > @@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart > This device tree matches the Spike ISA golden model as run with `spike -p1`. > > cpus { > + timebase-frequency = <1000000>; > cpu@0 { > device_type = "cpu"; > reg = <0x00000000>; -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog