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* [PATCHv2 0/3] Add LLCC support for SC7180 SoC
@ 2019-10-19 11:37 Sai Prakash Ranjan
  2019-10-19 11:37 ` [PATCHv2 1/3] soc: qcom: llcc: Add configuration data for SC7180 Sai Prakash Ranjan
                   ` (3 more replies)
  0 siblings, 4 replies; 15+ messages in thread
From: Sai Prakash Ranjan @ 2019-10-19 11:37 UTC (permalink / raw)
  To: Rob Herring, Mark Rutland, devicetree, Andy Gross,
	Bjorn Andersson, Stephen Boyd
  Cc: linux-arm-msm, linux-kernel, Rajendra Nayak, Rishabh Bhatnagar,
	Doug Anderson, Sai Prakash Ranjan

LLCC behaviour is controlled by the configuration data set
in the llcc-qcom driver, add the same for SC7180 SoC.
Also convert the existing bindings to json-schema and add
the compatible for SC7180 SoC.

v2:
 * Convert bindings to YAML and add compatible for SC7180
 * Address Stephen's comments on const

Sai Prakash Ranjan (2):
  dt-bindings: msm: Convert LLCC bindings to YAML
  dt-bindings: msm: Add LLCC for SC7180

Vivek Gautam (1):
  soc: qcom: llcc: Add configuration data for SC7180

 .../devicetree/bindings/arm/msm/qcom,llcc.txt | 41 --------------
 .../bindings/arm/msm/qcom,llcc.yaml           | 55 +++++++++++++++++++
 drivers/soc/qcom/llcc-qcom.c                  | 15 ++++-
 3 files changed, 69 insertions(+), 42 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCHv2 1/3] soc: qcom: llcc: Add configuration data for SC7180
  2019-10-19 11:37 [PATCHv2 0/3] Add LLCC support for SC7180 SoC Sai Prakash Ranjan
@ 2019-10-19 11:37 ` Sai Prakash Ranjan
  2019-10-20 18:20   ` Stephen Boyd
  2019-10-19 11:37 ` [PATCHv2 2/3] dt-bindings: msm: Convert LLCC bindings to YAML Sai Prakash Ranjan
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 15+ messages in thread
From: Sai Prakash Ranjan @ 2019-10-19 11:37 UTC (permalink / raw)
  To: Rob Herring, Mark Rutland, devicetree, Andy Gross,
	Bjorn Andersson, Stephen Boyd
  Cc: linux-arm-msm, linux-kernel, Rajendra Nayak, Rishabh Bhatnagar,
	Doug Anderson, Vivek Gautam, Sai Prakash Ranjan

From: Vivek Gautam <vivek.gautam@codeaurora.org>

Add LLCC configuration data for SC7180 SoC which controls
LLCC behaviour.

Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/soc/qcom/llcc-qcom.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 4bd982a294ce..429b5a60a1ba 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -91,7 +91,14 @@ struct qcom_llcc_config {
 	int size;
 };
 
-static struct llcc_slice_config sdm845_data[] =  {
+static const struct llcc_slice_config sc7180_data[] =  {
+	{ LLCC_CPUSS,    1,  256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
+	{ LLCC_MDM,      8,  128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
+	{ LLCC_GPUHTW,   11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
+	{ LLCC_GPU,      12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
+};
+
+static const struct llcc_slice_config sdm845_data[] =  {
 	{ LLCC_CPUSS,    1,  2816, 1, 0, 0xffc, 0x2,   0, 0, 1, 1, 1 },
 	{ LLCC_VIDSC0,   2,  512,  2, 1, 0x0,   0x0f0, 0, 0, 1, 1, 0 },
 	{ LLCC_VIDSC1,   3,  512,  2, 1, 0x0,   0x0f0, 0, 0, 1, 1, 0 },
@@ -112,6 +119,11 @@ static struct llcc_slice_config sdm845_data[] =  {
 	{ LLCC_AUDHW,    22, 1024, 1, 1, 0xffc, 0x2,   0, 0, 1, 1, 0 },
 };
 
+static const struct qcom_llcc_config sc7180_cfg = {
+	.sct_data	= sc7180_data,
+	.size		= ARRAY_SIZE(sc7180_data),
+};
+
 static const struct qcom_llcc_config sdm845_cfg = {
 	.sct_data	= sdm845_data,
 	.size		= ARRAY_SIZE(sdm845_data),
@@ -485,6 +497,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id qcom_llcc_of_match[] = {
+	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
 	{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
 	{ }
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCHv2 2/3] dt-bindings: msm: Convert LLCC bindings to YAML
  2019-10-19 11:37 [PATCHv2 0/3] Add LLCC support for SC7180 SoC Sai Prakash Ranjan
  2019-10-19 11:37 ` [PATCHv2 1/3] soc: qcom: llcc: Add configuration data for SC7180 Sai Prakash Ranjan
@ 2019-10-19 11:37 ` Sai Prakash Ranjan
  2019-10-20 18:20   ` Stephen Boyd
  2019-10-19 11:37 ` [PATCHv2 3/3] dt-bindings: msm: Add LLCC for SC7180 Sai Prakash Ranjan
  2019-10-21  3:32 ` [PATCHv2 0/3] Add LLCC support for SC7180 SoC Bjorn Andersson
  3 siblings, 1 reply; 15+ messages in thread
From: Sai Prakash Ranjan @ 2019-10-19 11:37 UTC (permalink / raw)
  To: Rob Herring, Mark Rutland, devicetree, Andy Gross,
	Bjorn Andersson, Stephen Boyd
  Cc: linux-arm-msm, linux-kernel, Rajendra Nayak, Rishabh Bhatnagar,
	Doug Anderson, Sai Prakash Ranjan

Convert LLCC bindings to DT schema format using json-schema.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 .../devicetree/bindings/arm/msm/qcom,llcc.txt | 41 --------------
 .../bindings/arm/msm/qcom,llcc.yaml           | 54 +++++++++++++++++++
 2 files changed, 54 insertions(+), 41 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
deleted file mode 100644
index eaee06b2d8f2..000000000000
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-== Introduction==
-
-LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
-that can be shared by multiple clients. Clients here are different cores in the
-SOC, the idea is to minimize the local caches at the clients and migrate to
-common pool of memory. Cache memory is divided into partitions called slices
-which are assigned to clients. Clients can query the slice details, activate
-and deactivate them.
-
-Properties:
-- compatible:
-	Usage: required
-	Value type: <string>
-	Definition: must be "qcom,sdm845-llcc"
-
-- reg:
-	Usage: required
-	Value Type: <prop-encoded-array>
-	Definition: The first element specifies the llcc base start address and
-		    the size of the register region. The second element specifies
-		    the llcc broadcast base address and size of the register region.
-
-- reg-names:
-        Usage: required
-        Value Type: <stringlist>
-        Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".
-
-- interrupts:
-	Usage: required
-	Definition: The interrupt is associated with the llcc edac device.
-			It's used for llcc cache single and double bit error detection
-			and reporting.
-
-Example:
-
-	cache-controller@1100000 {
-		compatible = "qcom,sdm845-llcc";
-		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
-		reg-names = "llcc_base", "llcc_broadcast_base";
-		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
-	};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
new file mode 100644
index 000000000000..5ac90d101807
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Last Level Cache Controller
+
+maintainers:
+  - Rishabh Bhatnagar <rishabhb@codeaurora.org>
+  - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
+
+description: |
+  LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
+  that can be shared by multiple clients. Clients here are different cores in the
+  SoC, the idea is to minimize the local caches at the clients and migrate to
+  common pool of memory. Cache memory is divided into partitions called slices
+  which are assigned to clients. Clients can query the slice details, activate
+  and deactivate them.
+
+properties:
+  compatible:
+    enum:
+      - qcom,sdm845-llcc
+
+  reg:
+    items:
+      - description: LLCC base register region
+      - description: LLCC broadcast base register region
+
+  reg-names:
+    items:
+      - const: llcc_base
+      - const: llcc_broadcast_base
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    cache-controller@1100000 {
+      compatible = "qcom,sdm845-llcc";
+      reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+      reg-names = "llcc_base", "llcc_broadcast_base";
+      interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+    };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCHv2 3/3] dt-bindings: msm: Add LLCC for SC7180
  2019-10-19 11:37 [PATCHv2 0/3] Add LLCC support for SC7180 SoC Sai Prakash Ranjan
  2019-10-19 11:37 ` [PATCHv2 1/3] soc: qcom: llcc: Add configuration data for SC7180 Sai Prakash Ranjan
  2019-10-19 11:37 ` [PATCHv2 2/3] dt-bindings: msm: Convert LLCC bindings to YAML Sai Prakash Ranjan
@ 2019-10-19 11:37 ` Sai Prakash Ranjan
  2019-10-20 18:20   ` Stephen Boyd
  2019-10-21  3:32 ` [PATCHv2 0/3] Add LLCC support for SC7180 SoC Bjorn Andersson
  3 siblings, 1 reply; 15+ messages in thread
From: Sai Prakash Ranjan @ 2019-10-19 11:37 UTC (permalink / raw)
  To: Rob Herring, Mark Rutland, devicetree, Andy Gross,
	Bjorn Andersson, Stephen Boyd
  Cc: linux-arm-msm, linux-kernel, Rajendra Nayak, Rishabh Bhatnagar,
	Doug Anderson, Sai Prakash Ranjan

Add LLCC compatible for SC7180 SoC.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
index 5ac90d101807..558749065b97 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
@@ -21,6 +21,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,sc7180-llcc
       - qcom,sdm845-llcc
 
   reg:
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 1/3] soc: qcom: llcc: Add configuration data for SC7180
  2019-10-19 11:37 ` [PATCHv2 1/3] soc: qcom: llcc: Add configuration data for SC7180 Sai Prakash Ranjan
@ 2019-10-20 18:20   ` Stephen Boyd
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2019-10-20 18:20 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Mark Rutland, Rob Herring,
	Sai Prakash Ranjan, devicetree
  Cc: linux-arm-msm, linux-kernel, Rajendra Nayak, Rishabh Bhatnagar,
	Doug Anderson, Vivek Gautam, Sai Prakash Ranjan

Quoting Sai Prakash Ranjan (2019-10-19 04:37:11)
> From: Vivek Gautam <vivek.gautam@codeaurora.org>
> 
> Add LLCC configuration data for SC7180 SoC which controls
> LLCC behaviour.
> 
> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 2/3] dt-bindings: msm: Convert LLCC bindings to YAML
  2019-10-19 11:37 ` [PATCHv2 2/3] dt-bindings: msm: Convert LLCC bindings to YAML Sai Prakash Ranjan
@ 2019-10-20 18:20   ` Stephen Boyd
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2019-10-20 18:20 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Mark Rutland, Rob Herring,
	Sai Prakash Ranjan, devicetree
  Cc: linux-arm-msm, linux-kernel, Rajendra Nayak, Rishabh Bhatnagar,
	Doug Anderson, Sai Prakash Ranjan

Quoting Sai Prakash Ranjan (2019-10-19 04:37:12)
> Convert LLCC bindings to DT schema format using json-schema.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 3/3] dt-bindings: msm: Add LLCC for SC7180
  2019-10-19 11:37 ` [PATCHv2 3/3] dt-bindings: msm: Add LLCC for SC7180 Sai Prakash Ranjan
@ 2019-10-20 18:20   ` Stephen Boyd
  0 siblings, 0 replies; 15+ messages in thread
From: Stephen Boyd @ 2019-10-20 18:20 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Mark Rutland, Rob Herring,
	Sai Prakash Ranjan, devicetree
  Cc: linux-arm-msm, linux-kernel, Rajendra Nayak, Rishabh Bhatnagar,
	Doug Anderson, Sai Prakash Ranjan

Quoting Sai Prakash Ranjan (2019-10-19 04:37:13)
> Add LLCC compatible for SC7180 SoC.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 0/3] Add LLCC support for SC7180 SoC
  2019-10-19 11:37 [PATCHv2 0/3] Add LLCC support for SC7180 SoC Sai Prakash Ranjan
                   ` (2 preceding siblings ...)
  2019-10-19 11:37 ` [PATCHv2 3/3] dt-bindings: msm: Add LLCC for SC7180 Sai Prakash Ranjan
@ 2019-10-21  3:32 ` Bjorn Andersson
  2019-10-23 19:49   ` Rob Herring
  3 siblings, 1 reply; 15+ messages in thread
From: Bjorn Andersson @ 2019-10-21  3:32 UTC (permalink / raw)
  To: Sai Prakash Ranjan
  Cc: Rob Herring, Mark Rutland, devicetree, Andy Gross, Stephen Boyd,
	linux-arm-msm, linux-kernel, Rajendra Nayak, Rishabh Bhatnagar,
	Doug Anderson

On Sat 19 Oct 04:37 PDT 2019, Sai Prakash Ranjan wrote:

> LLCC behaviour is controlled by the configuration data set
> in the llcc-qcom driver, add the same for SC7180 SoC.
> Also convert the existing bindings to json-schema and add
> the compatible for SC7180 SoC.
> 

Thanks for the patches and thanks for the review Stephen. Series applied

Regards,
Bjorn

> v2:
>  * Convert bindings to YAML and add compatible for SC7180
>  * Address Stephen's comments on const
> 
> Sai Prakash Ranjan (2):
>   dt-bindings: msm: Convert LLCC bindings to YAML
>   dt-bindings: msm: Add LLCC for SC7180
> 
> Vivek Gautam (1):
>   soc: qcom: llcc: Add configuration data for SC7180
> 
>  .../devicetree/bindings/arm/msm/qcom,llcc.txt | 41 --------------
>  .../bindings/arm/msm/qcom,llcc.yaml           | 55 +++++++++++++++++++
>  drivers/soc/qcom/llcc-qcom.c                  | 15 ++++-
>  3 files changed, 69 insertions(+), 42 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
> 
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 0/3] Add LLCC support for SC7180 SoC
  2019-10-21  3:32 ` [PATCHv2 0/3] Add LLCC support for SC7180 SoC Bjorn Andersson
@ 2019-10-23 19:49   ` Rob Herring
  2019-10-24 11:00     ` Sai Prakash Ranjan
  0 siblings, 1 reply; 15+ messages in thread
From: Rob Herring @ 2019-10-23 19:49 UTC (permalink / raw)
  To: Bjorn Andersson, Sai Prakash Ranjan
  Cc: Mark Rutland, devicetree, Andy Gross, Stephen Boyd,
	linux-arm-msm, linux-kernel, Rajendra Nayak, Rishabh Bhatnagar,
	Doug Anderson

On Sun, Oct 20, 2019 at 10:32 PM Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
>
> On Sat 19 Oct 04:37 PDT 2019, Sai Prakash Ranjan wrote:
>
> > LLCC behaviour is controlled by the configuration data set
> > in the llcc-qcom driver, add the same for SC7180 SoC.
> > Also convert the existing bindings to json-schema and add
> > the compatible for SC7180 SoC.
> >
>
> Thanks for the patches and thanks for the review Stephen. Series applied

And they break dt_binding_check. Please fix.

Rob

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 0/3] Add LLCC support for SC7180 SoC
  2019-10-23 19:49   ` Rob Herring
@ 2019-10-24 11:00     ` Sai Prakash Ranjan
  2019-10-24 22:33       ` Rob Herring
  0 siblings, 1 reply; 15+ messages in thread
From: Sai Prakash Ranjan @ 2019-10-24 11:00 UTC (permalink / raw)
  To: Rob Herring
  Cc: Bjorn Andersson, Mark Rutland, devicetree, Andy Gross,
	Stephen Boyd, linux-arm-msm, linux-kernel, Rajendra Nayak,
	Rishabh Bhatnagar, Doug Anderson, linux-arm-msm-owner

Hi Rob,

On 2019-10-24 01:19, Rob Herring wrote:
> On Sun, Oct 20, 2019 at 10:32 PM Bjorn Andersson
> <bjorn.andersson@linaro.org> wrote:
>> 
>> On Sat 19 Oct 04:37 PDT 2019, Sai Prakash Ranjan wrote:
>> 
>> > LLCC behaviour is controlled by the configuration data set
>> > in the llcc-qcom driver, add the same for SC7180 SoC.
>> > Also convert the existing bindings to json-schema and add
>> > the compatible for SC7180 SoC.
>> >
>> 
>> Thanks for the patches and thanks for the review Stephen. Series 
>> applied
> 
> And they break dt_binding_check. Please fix.
> 

I did check this and think that the error log from dt_binding_check is 
not valid because it says cache-level is a required property [1], but 
there is no such property in LLCC bindings.

[1] - http://patchwork.ozlabs.org/patch/1179800/

-Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 0/3] Add LLCC support for SC7180 SoC
  2019-10-24 11:00     ` Sai Prakash Ranjan
@ 2019-10-24 22:33       ` Rob Herring
  2019-10-25  7:54         ` Sai Prakash Ranjan
  0 siblings, 1 reply; 15+ messages in thread
From: Rob Herring @ 2019-10-24 22:33 UTC (permalink / raw)
  To: Sai Prakash Ranjan
  Cc: Bjorn Andersson, Mark Rutland, devicetree, Andy Gross,
	Stephen Boyd, linux-arm-msm, linux-kernel, Rajendra Nayak,
	Rishabh Bhatnagar, Doug Anderson, linux-arm-msm-owner

On Thu, Oct 24, 2019 at 6:00 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> Hi Rob,
>
> On 2019-10-24 01:19, Rob Herring wrote:
> > On Sun, Oct 20, 2019 at 10:32 PM Bjorn Andersson
> > <bjorn.andersson@linaro.org> wrote:
> >>
> >> On Sat 19 Oct 04:37 PDT 2019, Sai Prakash Ranjan wrote:
> >>
> >> > LLCC behaviour is controlled by the configuration data set
> >> > in the llcc-qcom driver, add the same for SC7180 SoC.
> >> > Also convert the existing bindings to json-schema and add
> >> > the compatible for SC7180 SoC.
> >> >
> >>
> >> Thanks for the patches and thanks for the review Stephen. Series
> >> applied
> >
> > And they break dt_binding_check. Please fix.
> >
>
> I did check this and think that the error log from dt_binding_check is
> not valid because it says cache-level is a required property [1], but
> there is no such property in LLCC bindings.

Then you should point out the issue and not just submit stuff ignoring
it. It has to be resolved one way or another.

If you refer to the DT spec[1], cache-level is required. The schema is
just enforcing that now. It's keying off the node name of
'cache-controller'.

Rob

[1] https://github.com/devicetree-org/devicetree-specification/blob/master/source/devicenodes.rst#multi-level-and-shared-cache-nodes-cpuscpul-cache

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 0/3] Add LLCC support for SC7180 SoC
  2019-10-24 22:33       ` Rob Herring
@ 2019-10-25  7:54         ` Sai Prakash Ranjan
  2019-11-13 15:00           ` Sai Prakash Ranjan
  0 siblings, 1 reply; 15+ messages in thread
From: Sai Prakash Ranjan @ 2019-10-25  7:54 UTC (permalink / raw)
  To: Rob Herring
  Cc: Bjorn Andersson, Mark Rutland, devicetree, Andy Gross,
	Stephen Boyd, linux-arm-msm, linux-kernel, Rajendra Nayak,
	Rishabh Bhatnagar, Doug Anderson, linux-arm-msm-owner

On 2019-10-25 04:03, Rob Herring wrote:
> On Thu, Oct 24, 2019 at 6:00 AM Sai Prakash Ranjan
> <saiprakash.ranjan@codeaurora.org> wrote:
>> 
>> Hi Rob,
>> 
>> On 2019-10-24 01:19, Rob Herring wrote:
>> > On Sun, Oct 20, 2019 at 10:32 PM Bjorn Andersson
>> > <bjorn.andersson@linaro.org> wrote:
>> >>
>> >> On Sat 19 Oct 04:37 PDT 2019, Sai Prakash Ranjan wrote:
>> >>
>> >> > LLCC behaviour is controlled by the configuration data set
>> >> > in the llcc-qcom driver, add the same for SC7180 SoC.
>> >> > Also convert the existing bindings to json-schema and add
>> >> > the compatible for SC7180 SoC.
>> >> >
>> >>
>> >> Thanks for the patches and thanks for the review Stephen. Series
>> >> applied
>> >
>> > And they break dt_binding_check. Please fix.
>> >
>> 
>> I did check this and think that the error log from dt_binding_check is
>> not valid because it says cache-level is a required property [1], but
>> there is no such property in LLCC bindings.
> 
> Then you should point out the issue and not just submit stuff ignoring
> it. It has to be resolved one way or another.
> 

I did not ignore it. When I ran the dt-binding check locally, it did not
error out and just passed on [1] and it was my bad that I did not check
the entire build logs to see if llcc dt binding check had some warning 
or
not. But this is the usual case where most of us don't look at the 
entire
build logs to check if there is a warning or not. We notice if there is 
an
immediate exit/fail in case of some warning/error. So it would be good 
if
we fail the dt-binding check build if there is some warning/error or 
atleast
provide some option to strict build to fail on warning, maybe there is 
already
a flag to do this?

After submitting the patch, I noticed this build failure on
patchwork.ozlabs.org and was waiting for your reply.

[1] https://paste.ubuntu.com/p/jNK8yfVkMG/

> If you refer to the DT spec[1], cache-level is required. The schema is
> just enforcing that now. It's keying off the node name of
> 'cache-controller'.
> 

This is not L2 or L3 cache, this is a system cache (last level cache) 
shared by
clients other than just CPU. So I don't know how do we specify 
cache-level for
this, let me know if you have some pointers.

-Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 0/3] Add LLCC support for SC7180 SoC
  2019-10-25  7:54         ` Sai Prakash Ranjan
@ 2019-11-13 15:00           ` Sai Prakash Ranjan
  2019-11-14 16:49             ` Stephen Boyd
  0 siblings, 1 reply; 15+ messages in thread
From: Sai Prakash Ranjan @ 2019-11-13 15:00 UTC (permalink / raw)
  To: Rob Herring
  Cc: Bjorn Andersson, Mark Rutland, devicetree, Andy Gross,
	Stephen Boyd, linux-arm-msm, linux-kernel, Rajendra Nayak,
	Rishabh Bhatnagar, Doug Anderson, linux-arm-msm-owner

Hello Rob,

On 2019-10-25 13:24, Sai Prakash Ranjan wrote:
> On 2019-10-25 04:03, Rob Herring wrote:
>> On Thu, Oct 24, 2019 at 6:00 AM Sai Prakash Ranjan
>> <saiprakash.ranjan@codeaurora.org> wrote:
>>> 
>>> Hi Rob,
>>> 
>>> On 2019-10-24 01:19, Rob Herring wrote:
>>> > On Sun, Oct 20, 2019 at 10:32 PM Bjorn Andersson
>>> > <bjorn.andersson@linaro.org> wrote:
>>> >>
>>> >> On Sat 19 Oct 04:37 PDT 2019, Sai Prakash Ranjan wrote:
>>> >>
>>> >> > LLCC behaviour is controlled by the configuration data set
>>> >> > in the llcc-qcom driver, add the same for SC7180 SoC.
>>> >> > Also convert the existing bindings to json-schema and add
>>> >> > the compatible for SC7180 SoC.
>>> >> >
>>> >>
>>> >> Thanks for the patches and thanks for the review Stephen. Series
>>> >> applied
>>> >
>>> > And they break dt_binding_check. Please fix.
>>> >
>>> 
>>> I did check this and think that the error log from dt_binding_check 
>>> is
>>> not valid because it says cache-level is a required property [1], but
>>> there is no such property in LLCC bindings.
>> 
>> Then you should point out the issue and not just submit stuff ignoring
>> it. It has to be resolved one way or another.
>> 
> 
> I did not ignore it. When I ran the dt-binding check locally, it did 
> not
> error out and just passed on [1] and it was my bad that I did not check
> the entire build logs to see if llcc dt binding check had some warning 
> or
> not. But this is the usual case where most of us don't look at the 
> entire
> build logs to check if there is a warning or not. We notice if there is 
> an
> immediate exit/fail in case of some warning/error. So it would be good 
> if
> we fail the dt-binding check build if there is some warning/error or 
> atleast
> provide some option to strict build to fail on warning, maybe there is 
> already
> a flag to do this?
> 
> After submitting the patch, I noticed this build failure on
> patchwork.ozlabs.org and was waiting for your reply.
> 
> [1] https://paste.ubuntu.com/p/jNK8yfVkMG/
> 
>> If you refer to the DT spec[1], cache-level is required. The schema is
>> just enforcing that now. It's keying off the node name of
>> 'cache-controller'.
>> 
> 
> This is not L2 or L3 cache, this is a system cache (last level cache) 
> shared by
> clients other than just CPU. So I don't know how do we specify 
> cache-level for
> this, let me know if you have some pointers.
> 

Any ideas on specifying the cache-level for system cache? Does 
dt-binding-check
needs to be updated for this case?

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 0/3] Add LLCC support for SC7180 SoC
  2019-11-13 15:00           ` Sai Prakash Ranjan
@ 2019-11-14 16:49             ` Stephen Boyd
  2019-11-15 11:24               ` Sai Prakash Ranjan
  0 siblings, 1 reply; 15+ messages in thread
From: Stephen Boyd @ 2019-11-14 16:49 UTC (permalink / raw)
  To: Rob Herring, Sai Prakash Ranjan
  Cc: Bjorn Andersson, Mark Rutland, devicetree, Andy Gross,
	linux-arm-msm, linux-kernel, Rajendra Nayak, Rishabh Bhatnagar,
	Doug Anderson, linux-arm-msm-owner

Quoting Sai Prakash Ranjan (2019-11-13 07:00:40)
> Hello Rob,
> 
> On 2019-10-25 13:24, Sai Prakash Ranjan wrote:
> > On 2019-10-25 04:03, Rob Herring wrote:
> >> On Thu, Oct 24, 2019 at 6:00 AM Sai Prakash Ranjan
> >> <saiprakash.ranjan@codeaurora.org> wrote:
> >>> 
> >>> Hi Rob,
> >>> 
> >>> On 2019-10-24 01:19, Rob Herring wrote:
> >>> > On Sun, Oct 20, 2019 at 10:32 PM Bjorn Andersson
> >>> > <bjorn.andersson@linaro.org> wrote:
> >>> >>
> >>> >> On Sat 19 Oct 04:37 PDT 2019, Sai Prakash Ranjan wrote:
> >>> >>
> >>> >> > LLCC behaviour is controlled by the configuration data set
> >>> >> > in the llcc-qcom driver, add the same for SC7180 SoC.
> >>> >> > Also convert the existing bindings to json-schema and add
> >>> >> > the compatible for SC7180 SoC.
> >>> >> >
> >>> >>
> >>> >> Thanks for the patches and thanks for the review Stephen. Series
> >>> >> applied
> >>> >
> >>> > And they break dt_binding_check. Please fix.
> >>> >
> >>> 
> >>> I did check this and think that the error log from dt_binding_check 
> >>> is
> >>> not valid because it says cache-level is a required property [1], but
> >>> there is no such property in LLCC bindings.
> >> 
> >> Then you should point out the issue and not just submit stuff ignoring
> >> it. It has to be resolved one way or another.
> >> 
> > 
> > I did not ignore it. When I ran the dt-binding check locally, it did 
> > not
> > error out and just passed on [1] and it was my bad that I did not check
> > the entire build logs to see if llcc dt binding check had some warning 
> > or
> > not. But this is the usual case where most of us don't look at the 
> > entire
> > build logs to check if there is a warning or not. We notice if there is 
> > an
> > immediate exit/fail in case of some warning/error. So it would be good 
> > if
> > we fail the dt-binding check build if there is some warning/error or 
> > atleast
> > provide some option to strict build to fail on warning, maybe there is 
> > already
> > a flag to do this?
> > 
> > After submitting the patch, I noticed this build failure on
> > patchwork.ozlabs.org and was waiting for your reply.
> > 
> > [1] https://paste.ubuntu.com/p/jNK8yfVkMG/
> > 
> >> If you refer to the DT spec[1], cache-level is required. The schema is
> >> just enforcing that now. It's keying off the node name of
> >> 'cache-controller'.
> >> 
> > 
> > This is not L2 or L3 cache, this is a system cache (last level cache) 
> > shared by
> > clients other than just CPU. So I don't know how do we specify 
> > cache-level for
> > this, let me know if you have some pointers.
> > 
> 
> Any ideas on specifying the cache-level for system cache? Does 
> dt-binding-check
> needs to be updated for this case?
> 

I don't see how 'cache-level' fits here. Maybe the node name should be
changed to 'system-cache-controller' and then the schema checker can
skip it?


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCHv2 0/3] Add LLCC support for SC7180 SoC
  2019-11-14 16:49             ` Stephen Boyd
@ 2019-11-15 11:24               ` Sai Prakash Ranjan
  0 siblings, 0 replies; 15+ messages in thread
From: Sai Prakash Ranjan @ 2019-11-15 11:24 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Rob Herring, Bjorn Andersson, Mark Rutland, devicetree,
	Andy Gross, linux-arm-msm, linux-kernel, Rajendra Nayak,
	Rishabh Bhatnagar, Doug Anderson, linux-arm-msm-owner

On 2019-11-14 22:19, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2019-11-13 07:00:40)
>> Hello Rob,
>> 
>> On 2019-10-25 13:24, Sai Prakash Ranjan wrote:
>> > On 2019-10-25 04:03, Rob Herring wrote:
>> >> On Thu, Oct 24, 2019 at 6:00 AM Sai Prakash Ranjan
>> >> <saiprakash.ranjan@codeaurora.org> wrote:
>> >>>
>> >>> Hi Rob,
>> >>>
>> >>> On 2019-10-24 01:19, Rob Herring wrote:
>> >>> > On Sun, Oct 20, 2019 at 10:32 PM Bjorn Andersson
>> >>> > <bjorn.andersson@linaro.org> wrote:
>> >>> >>
>> >>> >> On Sat 19 Oct 04:37 PDT 2019, Sai Prakash Ranjan wrote:
>> >>> >>
>> >>> >> > LLCC behaviour is controlled by the configuration data set
>> >>> >> > in the llcc-qcom driver, add the same for SC7180 SoC.
>> >>> >> > Also convert the existing bindings to json-schema and add
>> >>> >> > the compatible for SC7180 SoC.
>> >>> >> >
>> >>> >>
>> >>> >> Thanks for the patches and thanks for the review Stephen. Series
>> >>> >> applied
>> >>> >
>> >>> > And they break dt_binding_check. Please fix.
>> >>> >
>> >>>
>> >>> I did check this and think that the error log from dt_binding_check
>> >>> is
>> >>> not valid because it says cache-level is a required property [1], but
>> >>> there is no such property in LLCC bindings.
>> >>
>> >> Then you should point out the issue and not just submit stuff ignoring
>> >> it. It has to be resolved one way or another.
>> >>
>> >
>> > I did not ignore it. When I ran the dt-binding check locally, it did
>> > not
>> > error out and just passed on [1] and it was my bad that I did not check
>> > the entire build logs to see if llcc dt binding check had some warning
>> > or
>> > not. But this is the usual case where most of us don't look at the
>> > entire
>> > build logs to check if there is a warning or not. We notice if there is
>> > an
>> > immediate exit/fail in case of some warning/error. So it would be good
>> > if
>> > we fail the dt-binding check build if there is some warning/error or
>> > atleast
>> > provide some option to strict build to fail on warning, maybe there is
>> > already
>> > a flag to do this?
>> >
>> > After submitting the patch, I noticed this build failure on
>> > patchwork.ozlabs.org and was waiting for your reply.
>> >
>> > [1] https://paste.ubuntu.com/p/jNK8yfVkMG/
>> >
>> >> If you refer to the DT spec[1], cache-level is required. The schema is
>> >> just enforcing that now. It's keying off the node name of
>> >> 'cache-controller'.
>> >>
>> >
>> > This is not L2 or L3 cache, this is a system cache (last level cache)
>> > shared by
>> > clients other than just CPU. So I don't know how do we specify
>> > cache-level for
>> > this, let me know if you have some pointers.
>> >
>> 
>> Any ideas on specifying the cache-level for system cache? Does
>> dt-binding-check
>> needs to be updated for this case?
>> 
> 
> I don't see how 'cache-level' fits here. Maybe the node name should be
> changed to 'system-cache-controller' and then the schema checker can
> skip it?

Sounds good and correct. I made this change and ran the dt binding check
and no warning was observed.

Sent a patch - 
https://lore.kernel.org/lkml/cover.1573814758.git.saiprakash.ranjan@codeaurora.org/

-Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2019-11-15 11:24 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-19 11:37 [PATCHv2 0/3] Add LLCC support for SC7180 SoC Sai Prakash Ranjan
2019-10-19 11:37 ` [PATCHv2 1/3] soc: qcom: llcc: Add configuration data for SC7180 Sai Prakash Ranjan
2019-10-20 18:20   ` Stephen Boyd
2019-10-19 11:37 ` [PATCHv2 2/3] dt-bindings: msm: Convert LLCC bindings to YAML Sai Prakash Ranjan
2019-10-20 18:20   ` Stephen Boyd
2019-10-19 11:37 ` [PATCHv2 3/3] dt-bindings: msm: Add LLCC for SC7180 Sai Prakash Ranjan
2019-10-20 18:20   ` Stephen Boyd
2019-10-21  3:32 ` [PATCHv2 0/3] Add LLCC support for SC7180 SoC Bjorn Andersson
2019-10-23 19:49   ` Rob Herring
2019-10-24 11:00     ` Sai Prakash Ranjan
2019-10-24 22:33       ` Rob Herring
2019-10-25  7:54         ` Sai Prakash Ranjan
2019-11-13 15:00           ` Sai Prakash Ranjan
2019-11-14 16:49             ` Stephen Boyd
2019-11-15 11:24               ` Sai Prakash Ranjan

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