From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 122ABC432C3 for ; Thu, 14 Nov 2019 22:50:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D5E23206EF for ; Thu, 14 Nov 2019 22:50:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="IQttiHaA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727063AbfKNWuW (ORCPT ); Thu, 14 Nov 2019 17:50:22 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:41204 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726319AbfKNWuV (ORCPT ); Thu, 14 Nov 2019 17:50:21 -0500 Received: by mail-pg1-f193.google.com with SMTP id h4so4706471pgv.8 for ; Thu, 14 Nov 2019 14:50:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=message-id:mime-version:content-transfer-encoding:in-reply-to :references:cc:to:subject:from:user-agent:date; bh=fV40oETXjKcGlIr1gGKnzSoiYzzgILYSSWxjfebyNP8=; b=IQttiHaAJGKACK5iLQHgc60JB1JPMzLpLI1DfqpXl7axGbV2ULuY8eJUGc9Qoado47 UGVaSRRH1bnSNoxedmuguxdiav53vPa3kaEGVLaAQ3wkPsnqskxDHoBu+bPY/30ZD8PK nr9n7pQ3Ltf+Jy66JShXkhoWL328ExLRzYYu4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:message-id:mime-version :content-transfer-encoding:in-reply-to:references:cc:to:subject:from :user-agent:date; bh=fV40oETXjKcGlIr1gGKnzSoiYzzgILYSSWxjfebyNP8=; b=Fm0aHEHHXkxeSP0KWoAKunI0VS5ajNOm/JWwSw6bDLE5G37NS0ZBGdqvK/kxBOwjUp iElCmhCnyyUGx78/uYf6nsAzfjkZjUy2letLDJtUsWluGIUke49wpjcnchhrreOpjkyp /70L7v397v5LLiNjR2MLb6AzBwPA6jAbM1GxJyZpp/SOFlluEQMWqbVVNOAeRndwahfS 92g+A6kLtd1X/HVxac2CJ942irVvxsBqI0Dwp0c5u2YtuiXMd5ae7LPY3IHq12uWc2rE rDLEu/viNXMmY+m0wCe50kLy16SU/r1a3H1QNv4WRqfFONNM1je5cvCUC7IwdFZM9N4a oy9w== X-Gm-Message-State: APjAAAU7bqEoDV1/O2UMdTYuyw1fcmXLspBtmJ26Or/6x6k2r/XkShh6 28LIHXQEwEXtkyMufYSWTmUYIQ== X-Google-Smtp-Source: APXvYqwGZF0CNHJX1S5Aa2rAAxaMTnHOr5W0JJN8PB1EeZukU4bqr9Ehf1A2qoVMQcXBra2LOY9T8Q== X-Received: by 2002:a17:90b:d8e:: with SMTP id bg14mr14990905pjb.26.1573771818995; Thu, 14 Nov 2019 14:50:18 -0800 (PST) Received: from chromium.org ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id u207sm9215633pfc.127.2019.11.14.14.50.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 14:50:18 -0800 (PST) Message-ID: <5dcdda2a.1c69fb81.27852.ac35@mx.google.com> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <4b949a4f401a7f9d403ed0f0c16c7feb083f3524.1573499020.git.amit.kucheria@linaro.org> References: <4b949a4f401a7f9d403ed0f0c16c7feb083f3524.1573499020.git.amit.kucheria@linaro.org> Cc: Daniel Lezcano , Amit Kucheria , linux-pm@vger.kernel.org To: Amit Kucheria , Andy Gross , bjorn.andersson@linaro.org, edubezval@gmail.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, sivaa@codeaurora.org Subject: Re: [PATCH 1/3] drivers: thermal: tsens: Add critical interrupt support From: Stephen Boyd User-Agent: alot/0.8.1 Date: Thu, 14 Nov 2019 14:50:17 -0800 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Amit Kucheria (2019-11-11 11:21:27) > diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/t= sens-common.c > index 4359a4247ac3..2989cb952cdb 100644 > --- a/drivers/thermal/qcom/tsens-common.c > +++ b/drivers/thermal/qcom/tsens-common.c > @@ -321,6 +357,65 @@ static inline u32 masked_irq(u32 hw_id, u32 mask, en= um tsens_ver ver) > return 0; > } > =20 > +/** > + * tsens_critical_irq_thread - Threaded interrupt handler for critical i= nterrupts > + * @irq: irq number > + * @data: tsens controller private data > + * > + * Check all sensors to find ones that violated their critical threshold= limits. > + * Clear and then re-enable the interrupt. > + * > + * The level-triggered interrupt might deassert if the temperature retur= ned to > + * within the threshold limits by the time the handler got scheduled. We > + * consider the irq to have been handled in that case. > + * > + * Return: IRQ_HANDLED > + */ > +irqreturn_t tsens_critical_irq_thread(int irq, void *data) > +{ > + struct tsens_priv *priv =3D data; > + struct tsens_irq_data d; > + bool enable =3D true, disable =3D false; Why not just use true and false in the one place these variables are used? > + unsigned long flags; > + int temp, ret, i; > + > + for (i =3D 0; i < priv->num_sensors; i++) { > + struct tsens_sensor *s =3D &priv->sensor[i]; Maybe make this const? > + u32 hw_id =3D s->hw_id; > + > + if (IS_ERR(priv->sensor[i].tzd)) IS_ERR(s->tzd)? > + continue; > + if (!tsens_threshold_violated(priv, hw_id, &d)) > + continue; > + ret =3D get_temp_tsens_valid(s, &temp); Can this accept a const 's'? > + if (ret) { > + dev_err(priv->dev, "[%u] %s: error reading sensor= \n", hw_id, __func__); > + continue; > + } > + > + spin_lock_irqsave(&priv->ul_lock, flags); > + > + tsens_read_irq_state(priv, hw_id, s, &d); > + > + if (d.crit_viol && > + !masked_irq(hw_id, d.crit_irq_mask, tsens_version(pri= v))) { > + tsens_set_interrupt(priv, hw_id, CRITICAL, disabl= e); > + if (d.crit_thresh > temp) { > + dev_dbg(priv->dev, "[%u] %s: re-arm upper= \n", > + priv->sensor[i].hw_id, __func__); hw_id instead of priv->sensor...? > + } else { > + dev_dbg(priv->dev, "[%u] %s: TZ update tr= igger (%d mC)\n", > + hw_id, __func__, temp); > + } > + tsens_set_interrupt(priv, hw_id, CRITICAL, enable= ); > + } > + > + spin_unlock_irqrestore(&priv->crit_lock, flags); > + } > + > + return IRQ_HANDLED; > +} > + > /** > * tsens_irq_thread - Threaded interrupt handler for uplow interrupts > * @irq: irq number > diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c > index 7d317660211e..784c4976c4f9 100644 > --- a/drivers/thermal/qcom/tsens.c > +++ b/drivers/thermal/qcom/tsens.c > @@ -121,6 +121,27 @@ static int tsens_register(struct tsens_priv *priv) > =20 > enable_irq_wake(irq); > =20 > + if (tsens_version(priv) > VER_1_X) { > + irq =3D platform_get_irq_byname(pdev, "critical"); > + if (irq < 0) { > + ret =3D irq; > + goto err_put_device; > + } > + > + ret =3D devm_request_threaded_irq(&pdev->dev, irq, > + NULL, tsens_critical_irq_= thread, > + IRQF_TRIGGER_HIGH | IRQF_= ONESHOT, > + dev_name(&pdev->dev), pri= v); > + if (ret) { > + dev_err(&pdev->dev, "%s: failed to get critical i= rq\n", __func__); > + goto err_put_device; Do we need to disable_irq_wake() for the previous irq here? > + } > + > + enable_irq_wake(irq); > + } > + > + return 0; > + > err_put_device: > put_device(&pdev->dev); > return ret;