From: Shunyong Yang <shunyong.yang@hxt-semitech.com>
To: <bhelgaas@google.com>
Cc: <okaya@kernel.org>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Shunyong Yang <shunyong.yang@hxt-semitech.com>,
Joey Zheng <yu.zheng@hxt-semitech.com>
Subject: [PATCH v2 2/2] PCI: pciehp: Add HXT quirk for Command Completed errata
Date: Wed, 7 Nov 2018 15:25:05 +0800 [thread overview]
Message-ID: <5e88860c8426df537c5a5f2d0e6add6df8955a0f.1541574331.git.shunyong.yang@hxt-semitech.com> (raw)
In-Reply-To: <bcaf1d5d-23a6-d4e6-08e8-587daf6cca06@kernel.org>
The HXT SD4800 PCI controller does not set the Command Completed
bit unless writes to the Slot Command register change "Control"
bits.
This patch adds SD4800 to the quirk.
Cc: Joey Zheng <yu.zheng@hxt-semitech.com>
Signed-off-by: Shunyong Yang <shunyong.yang@hxt-semitech.com>
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 7dd443aea5a5..91db67963aea 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -920,3 +920,5 @@ static void quirk_cmd_compl(struct pci_dev *pdev)
PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
+ PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
--
1.8.3.1
next prev parent reply other threads:[~2018-11-07 7:25 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-05 3:15 [PATCH] PCI: Add HXT vendor ID and ACS quirk Shunyong Yang
2018-11-05 23:12 ` Sinan Kaya
2018-11-06 1:34 ` Yang, Shunyong
2018-11-07 7:24 ` [PATCH v2 1/2] " Shunyong Yang
2019-02-01 23:19 ` Bjorn Helgaas
2019-02-11 0:52 ` Yang, Shunyong
2022-02-10 22:53 ` Bjorn Helgaas
2018-11-07 7:25 ` Shunyong Yang [this message]
2018-11-19 1:07 ` [PATCH v2 2/2] PCI: pciehp: Add HXT quirk for Command Completed errata Yang, Shunyong
2018-12-07 2:31 ` Yang, Shunyong
2018-11-19 16:16 ` Keith Busch
2018-11-20 10:19 ` Yang, Shunyong
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