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Tue, 14 Jul 2020 10:43:42 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 58C71C433A0; Tue, 14 Jul 2020 10:43:42 +0000 (UTC) Received: from [192.168.29.129] (unknown [49.36.75.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mkshah) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6D7C5C43387; Tue, 14 Jul 2020 10:43:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6D7C5C43387 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=mkshah@codeaurora.org Subject: Re: [PATCH v3 2/5] pinctrl: qcom: Add msmgpio irqchip flags To: Doug Anderson Cc: Bjorn Andersson , Marc Zyngier , LinusW , Stephen Boyd , Evan Green , Matthias Kaehlcke , LKML , linux-arm-msm , "open list:GPIO SUBSYSTEM" , Andy Gross , Thomas Gleixner , Jason Cooper , Rajendra Nayak , Lina Iyer , Srinivas Rao L References: <1592818308-23001-1-git-send-email-mkshah@codeaurora.org> <1592818308-23001-3-git-send-email-mkshah@codeaurora.org> From: Maulik Shah Message-ID: <5f6c3eec-5c2c-d546-ac3c-65e7d25c9031@codeaurora.org> Date: Tue, 14 Jul 2020 16:13:33 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-GB Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 7/14/2020 3:47 AM, Doug Anderson wrote: > Hi, > > On Mon, Jun 22, 2020 at 2:32 AM Maulik Shah wrote: >> Add irqchip specific flags for msmgpio irqchip to mask non wakeirqs >> during suspend and mask before setting irq type. >> >> Masking before changing type should make sure any spurious interrupt >> is not detected during this operation. >> >> Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") >> Acked-by: Linus Walleij >> Signed-off-by: Maulik Shah >> --- >> drivers/pinctrl/qcom/pinctrl-msm.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c >> index 2419023..b909ffe 100644 >> --- a/drivers/pinctrl/qcom/pinctrl-msm.c >> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c >> @@ -1143,6 +1143,8 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) >> pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; >> pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity; >> pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity; >> + pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND > I haven't tested it, but with my suggestion in patch #4 to use > irq_suspend and irq_resume, I presume adding IRQCHIP_MASK_ON_SUSPEND > is no longer needed? it will still be needed, to let the non wakeup capable IRQ masked during suspend. > > >> + | IRQCHIP_SET_TYPE_MASKED; > IIUC adding "IRQCHIP_SET_TYPE_MASKED" is unrelated to the rest of this > series, right? Right, but since we are adding missing flags, i added it together. Thanks, Maulik > > -Doug -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation