From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75237C43334 for ; Fri, 15 Jul 2022 03:47:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232901AbiGODrW (ORCPT ); Thu, 14 Jul 2022 23:47:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229481AbiGODrU (ORCPT ); Thu, 14 Jul 2022 23:47:20 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74710774AB for ; Thu, 14 Jul 2022 20:47:18 -0700 (PDT) Received: from dggpemm500024.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4LkcgB6lkCzjWyZ; Fri, 15 Jul 2022 11:44:38 +0800 (CST) Received: from dggpemm500001.china.huawei.com (7.185.36.107) by dggpemm500024.china.huawei.com (7.185.36.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 15 Jul 2022 11:47:15 +0800 Received: from [10.67.111.195] (10.67.111.195) by dggpemm500001.china.huawei.com (7.185.36.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Fri, 15 Jul 2022 11:47:15 +0800 Subject: Re: [PATCH -next] riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit From: chenlifu To: , , , , , , , , References: <20220615014714.1650349-1-chenlifu@huawei.com> <11a0698c-5726-15e8-2448-3529d2d0b098@huawei.com> Message-ID: <606b1f5a-ea1e-f756-a00b-6b622238b453@huawei.com> Date: Fri, 15 Jul 2022 11:47:01 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.9.0 MIME-Version: 1.0 In-Reply-To: <11a0698c-5726-15e8-2448-3529d2d0b098@huawei.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.111.195] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500001.china.huawei.com (7.185.36.107) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >> Since commit 5d8544e2d007 ("RISC-V: Generic library routines and >> assembly") >> and commit ebcbd75e3962 ("riscv: Fix the bug in memory access fixup >> code"), >> if __clear_user and __copy_user return from an fixup branch, >> CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that >> S-mode memory accesses to pages that are accessible by U-mode will >> success. >> Disable S-mode access to U-mode memory should clear SR_SUM bit. >> >> Fixes: 5d8544e2d007 ("RISC-V: Generic library routines and assembly") >> Fixes: ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code") >> >> Signed-off-by: Chen Lifu >> --- >>   arch/riscv/lib/uaccess.S | 4 ++-- >>   1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S >> index 8c475f4da308..ec486e5369d9 100644 >> --- a/arch/riscv/lib/uaccess.S >> +++ b/arch/riscv/lib/uaccess.S >> @@ -173,11 +173,11 @@ ENTRY(__asm_copy_from_user) >>       ret >>       /* Exception fixup code */ >>   10: >>       /* Disable access to user memory */ >> -    csrs CSR_STATUS, t6 >> +    csrc CSR_STATUS, t6 >>       mv a0, t5 >>       ret >>   ENDPROC(__asm_copy_to_user) >>   ENDPROC(__asm_copy_from_user) >>   EXPORT_SYMBOL(__asm_copy_to_user) >> @@ -225,10 +225,10 @@ ENTRY(__clear_user) >>       j 3b >>       /* Exception fixup code */ >>   11: >>       /* Disable access to user memory */ >> -    csrs CSR_STATUS, t6 >> +    csrc CSR_STATUS, t6 >>       mv a0, a1 >>       ret >>   ENDPROC(__clear_user) >>   EXPORT_SYMBOL(__clear_user) >> > > friendly ping ... > friendly ping ... > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv > .