From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1753153AbcHZRlz (ORCPT <rfc822;w@1wt.eu>);
        Fri, 26 Aug 2016 13:41:55 -0400
Received: from smtprelay2.synopsys.com ([198.182.60.111]:60812 "EHLO
        smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1751223AbcHZRlw (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Fri, 26 Aug 2016 13:41:52 -0400
Subject: Re: [PATCH] arc: perf: Enable generic "cache-references" and
 "cache-misses" events
To: Alexey Brodkin <Alexey.Brodkin@synopsys.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Peter Zijlstra <a.p.zijlstra@chello.nl>
References: <1472125647-518-1-git-send-email-abrodkin@synopsys.com>
CC: "linux-snps-arc@lists.infradead.org" 
        <linux-snps-arc@lists.infradead.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Arnaldo Carvalho de Melo <acme@redhat.com>,
        "stable@vger.kernel.org" <stable@vger.kernel.org>
From: Vineet Gupta <Vineet.Gupta1@synopsys.com>
Message-ID: <6074e252-6e18-bb01-4de1-023bd7e82f03@synopsys.com>
Date: Fri, 26 Aug 2016 10:30:24 -0700
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101
 Thunderbird/45.2.0
MIME-Version: 1.0
In-Reply-To: <1472125647-518-1-git-send-email-abrodkin@synopsys.com>
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
X-Originating-IP: [10.9.129.73]
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 08/25/2016 04:49 AM, Alexey Brodkin wrote:
> ...
>  	[PERF_COUNT_ARC_EDTLB] = "edtlb",	/* D-TLB Miss */
>  	[PERF_COUNT_ARC_EITLB] = "eitlb",	/* I-TLB Miss */
> +
> +	[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc",	/* Instr: mem read cached */
> +	[PERF_COUNT_HW_CACHE_MISSES] = "dclm",		/* D-cache Load Miss */

I think this is duplicating a mistake we already have. I vaguely remember when
doing some hackbench profiling last year with range based profiling confined to
memset routine and saw that L1-dcache-misses was counting zero. This is because it
only counts LD misses while memset only does ST.

Performance counter stats for '/sbin/hackbench':

     0 L1-dcache-misses
     0 L1-dcache-load-misses
     1846082 L1-dcache-store-misses


@PeterZ do you concur that is wrong and we ought to setup 2 counters to do this
correctly ?

-Vineet