From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73294C43460 for ; Tue, 20 Apr 2021 08:30:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4413C6113C for ; Tue, 20 Apr 2021 08:30:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230517AbhDTIa4 (ORCPT ); Tue, 20 Apr 2021 04:30:56 -0400 Received: from szxga08-in.huawei.com ([45.249.212.255]:3342 "EHLO szxga08-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230495AbhDTIaz (ORCPT ); Tue, 20 Apr 2021 04:30:55 -0400 Received: from DGGEML402-HUB.china.huawei.com (unknown [172.30.72.57]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4FPcGg3sCZz14JV1; Tue, 20 Apr 2021 16:26:35 +0800 (CST) Received: from dggpeml500013.china.huawei.com (7.185.36.41) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server (TLS) id 14.3.498.0; Tue, 20 Apr 2021 16:30:21 +0800 Received: from [10.174.187.161] (10.174.187.161) by dggpeml500013.china.huawei.com (7.185.36.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Tue, 20 Apr 2021 16:30:20 +0800 Subject: Re: [PATCH v5 10/16] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled To: Like Xu , , Paolo Bonzini , Sean Christopherson References: <20210415032016.166201-1-like.xu@linux.intel.com> <20210415032016.166201-11-like.xu@linux.intel.com> CC: , , , , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , , , , "Fangyi (Eric)" , Xiexiangyou From: Liuxiangdong Message-ID: <607E911C.4090706@huawei.com> Date: Tue, 20 Apr 2021 16:30:20 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 MIME-Version: 1.0 In-Reply-To: <20210415032016.166201-11-like.xu@linux.intel.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.187.161] X-ClientProxiedBy: dggeme712-chm.china.huawei.com (10.1.199.108) To dggpeml500013.china.huawei.com (7.185.36.41) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021/4/15 11:20, Like Xu wrote: > The bit 12 represents "Processor Event Based Sampling Unavailable (RO)" : > 1 = PEBS is not supported. > 0 = PEBS is supported. > > A write to this PEBS_UNAVL available bit will bring #GP(0) when guest PEBS > is enabled. Some PEBS drivers in guest may care about this bit. > > Signed-off-by: Like Xu > --- > arch/x86/kvm/vmx/pmu_intel.c | 2 ++ > arch/x86/kvm/x86.c | 4 ++++ > 2 files changed, 6 insertions(+) > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > index 58f32a55cc2e..c846d3eef7a7 100644 > --- a/arch/x86/kvm/vmx/pmu_intel.c > +++ b/arch/x86/kvm/vmx/pmu_intel.c > @@ -588,6 +588,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) > bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1); > > if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) { > + vcpu->arch.ia32_misc_enable_msr &= ~MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; > if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_BASELINE) { > pmu->pebs_enable_mask = ~pmu->global_ctrl; > pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE; > @@ -597,6 +598,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) > } > pmu->pebs_data_cfg_mask = ~0xff00000full; > } else { > + vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; > pmu->pebs_enable_mask = > ~((1ull << pmu->nr_arch_gp_counters) - 1); > } I guess what we want is if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) { vcpu->arch.ia32_misc_enable_msr &= ~MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_BASELINE) { pmu->pebs_enable_mask = ~pmu->global_ctrl; pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE; for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { pmu->fixed_ctr_ctrl_mask &= ~(1ULL << (INTEL_PMC_IDX_FIXED + i * 4)); } pmu->pebs_data_cfg_mask = ~0xff00000full; } else { pmu->pebs_enable_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1); } } else { vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; vcpu->arch.perf_capabilities &= ~PERF_CAP_PEBS_MASK; } But here is if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) { vcpu->arch.ia32_misc_enable_msr &= ~MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_BASELINE) { pmu->pebs_enable_mask = ~pmu->global_ctrl; pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE; for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { pmu->fixed_ctr_ctrl_mask &= ~(1ULL << (INTEL_PMC_IDX_FIXED + i * 4)); } pmu->pebs_data_cfg_mask = ~0xff00000full; } else { vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL; pmu->pebs_enable_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1); } } else { vcpu->arch.perf_capabilities &= ~PERF_CAP_PEBS_MASK; } Wrong else branch? > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 1a64e816e06d..ed38f1dada63 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -3126,6 +3126,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > break; > case MSR_IA32_MISC_ENABLE: > data &= ~MSR_IA32_MISC_ENABLE_EMON; > + if (!msr_info->host_initiated && > + (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) && > + (data & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) > + return 1; > if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && > ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { > if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))