Re: [PATCH 4/4] KVM: SVM: Disable SEV-ES support if MMIO caching is disable

From: Kai Huang <kai.huang@intel.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	Michael Roth <michael.roth@amd.com>,
	Tom Lendacky <thomas.lendacky@amd.com>
Subject: Re: [PATCH 4/4] KVM: SVM: Disable SEV-ES support if MMIO caching is disable
Date: Mon, 01 Aug 2022 21:30:34 +1200	[thread overview]
Message-ID: <610ba489b8c0c03f7ac004049e10972bf01de927.camel@intel.com> (raw)
In-Reply-To: <YuP66QVxyeT4wd5H@google.com>

On Fri, 2022-07-29 at 15:21 +0000, Sean Christopherson wrote:
> On Fri, Jul 29, 2022, Kai Huang wrote:
> > On Thu, 2022-07-28 at 22:17 +0000, Sean Christopherson wrote:
> > > Disable SEV-ES if MMIO caching is disabled as SEV-ES relies on MMIO SPTEs
> > > generating #NPF(RSVD), which are reflected by the CPU into the guest as
> > > a #VC.  With SEV-ES, the untrusted host, a.k.a. KVM, doesn't have access
> > > to the guest instruction stream or register state and so can't directly
> > > emulate in response to a #NPF on an emulated MMIO GPA.  Disabling MMIO
> > > caching means guest accesses to emulated MMIO ranges cause #NPF(!PRESENT),
> > > and those flavors of #NPF cause automatic VM-Exits, not #VC.
> > > 
> > > Fixes: b09763da4dd8 ("KVM: x86/mmu: Add module param to disable MMIO caching (for testing)")
> > > Reported-by: Michael Roth <michael.roth@amd.com>
> > > Cc: Tom Lendacky <thomas.lendacky@amd.com>
> > > Cc: stable@vger.kernel.org
> > > Signed-off-by: Sean Christopherson <seanjc@google.com>
> > > ---
> 
> ...
> 
> > > +	/*
> > > +	 * SEV-ES requires MMIO caching as KVM doesn't have access to the guest
> > > +	 * instruction stream, i.e. can't emulate in response to a #NPF and
> > > +	 * instead relies on #NPF(RSVD) being reflected into the guest as #VC
> > > +	 * (the guest can then do a #VMGEXIT to request MMIO emulation).
> > > +	 */
> > > +	if (!enable_mmio_caching)
> > > +		goto out;
> > > +
> > > 
> > 
> > I am not familiar with SEV, but looks it is similar to TDX -- they both causes
> > #VE to guest instead of faulting into KVM.  And they both require explicit call
> > from guest to do MMIO.
> > 
> > In this case, does existing MMIO caching logic still apply to them?
> 
> Yes, because TDX/SEV-ES+ need to generate #VE/#VC on emulated MMIO so that legacy
> (or intentionally unenlightened) software in the guest doesn't simply hang/die on
> memory accesses to emulated MMIO (as opposed to direct TDVMCALL/#VMGEXIT).
> 
> > Should we still treat SEV and TDX's MMIO handling as MMIO caching being
> > enabled?  Or perhaps another variable?
> 
> I don't think a separate variable is necesary.  At its core, KVM is still caching
> MMIO GPAs via magic SPTE values.  The fact that it's required for functionality
> doesn't make the name wrong.

OK.

> 
> SEV-ES+ in particular doesn't have a strong guarantee that inducing #VC via #NPF(RSVD)
> is always possible.  Theoretically, an SEV-ES+ capable CPU could ship with an effective
> MAXPHYADDR=51 (after reducing the raw MAXPHYADDR) and C-bit=51, in which case there are
> no resered PA bits and thus no reserved PTE bits at all.  That's obviously unlikely to
> happen, but if it does come up, then disabling SEV-ES+ due to MMIO caching not being
> possible is the desired behavior, e.g. either the CPU configuration is bad or KVM is
> lacking support for a newfangled way to support emulated MMIO (in a future theoretical
> SEV-* product).

I bet AMD will see this (your) response and never ship such chips :)

-- 
Thanks,
-Kai