From: "Xu, Like" <like.xu@intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
eranian@google.com, andi@firstfloor.org,
kan.liang@linux.intel.com, wei.w.wang@intel.com,
Wanpeng Li <wanpengli@tencent.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, x86@kernel.org,
linux-kernel@vger.kernel.org, Andi Kleen <ak@linux.intel.com>,
Like Xu <like.xu@linux.intel.com>
Subject: Re: [PATCH v4 08/16] KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to manage guest DS buffer
Date: Thu, 8 Apr 2021 13:39:49 +0800 [thread overview]
Message-ID: <610bfd14-3250-0542-2d93-cbd15f2b4e16@intel.com> (raw)
In-Reply-To: <YG3SPsiFJPeXQXhq@hirez.programming.kicks-ass.net>
Hi Peter,
Thanks for your detailed comments.
If you have more comments for other patches, please let me know.
On 2021/4/7 23:39, Peter Zijlstra wrote:
> On Mon, Mar 29, 2021 at 01:41:29PM +0800, Like Xu wrote:
>> @@ -3869,10 +3876,12 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
>>
>> if (arr[1].guest)
>> arr[0].guest |= arr[1].guest;
>> - else
>> + else {
>> arr[1].guest = arr[1].host;
>> + arr[2].guest = arr[2].host;
>> + }
> What's all this gibberish?
>
> The way I read that it says:
>
> if guest has PEBS_ENABLED
> guest GLOBAL_CTRL |= PEBS_ENABLED
> otherwise
> guest PEBS_ENABLED = host PEBS_ENABLED
> guest DS_AREA = host DS_AREA
>
> which is just completely random garbage afaict. Why would you leak host
> msrs into the guest?
In fact, this is not a leak at all.
When we do "arr[i].guest = arr[i].host;" assignment in the
intel_guest_get_msrs(),
the KVM will check "if (msrs[i].host == msrs[i].guest)" and if so, it
disables the atomic
switch for this msr during vmx transaction in the caller
atomic_switch_perf_msrs().
In that case, the msr value doesn't change and any guest write will be trapped.
If the next check is "msrs[i].host != msrs[i].guest", the atomic switch
will be triggered again.
Compared to before, this part of the logic has not changed, which helps to
reduce overhead.
> Why would you change guest GLOBAL_CTRL implicitly;
This is because in the early part of this function, we have operations:
if (x86_pmu.flags & PMU_FL_PEBS_ALL)
arr[0].guest &= ~cpuc->pebs_enabled;
else
arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
and if guest has PEBS_ENABLED, we need these bits back for PEBS counters:
arr[0].guest |= arr[1].guest;
> guest had better wrmsr that himself to control when stuff is enabled.
When vm_entry, the msr value of GLOBAL_CTRL on the hardware may be
different from trapped value "pmu->global_ctrl" written by the guest.
If the perf scheduler cross maps guest counter X to the host counter Y,
we have to enable the bit Y in GLOBAL_CTRL before vm_entry rather than X.
>
> This just cannot be right.
next prev parent reply other threads:[~2021-04-08 5:40 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-29 5:41 [PATCH v4 00/16] KVM: x86/pmu: Add basic support to enable Guest PEBS via DS Like Xu
2021-03-29 5:41 ` [PATCH v4 01/16] perf/x86/intel: Add x86_pmu.pebs_vmx for Ice Lake Servers Like Xu
2021-04-06 3:24 ` Liuxiangdong (Aven, Cloud Infrastructure Service Product Dept.)
2021-04-06 5:14 ` Xu, Like
2021-04-08 1:40 ` Liuxiangdong (Aven, Cloud Infrastructure Service Product Dept.)
2021-04-09 8:33 ` Liuxiangdong (Aven, Cloud Infrastructure Service Product Dept.)
2021-04-09 8:46 ` Like Xu
2021-04-12 11:26 ` Liuxiangdong (Aven, Cloud Infrastructure Service Product Dept.)
2021-04-12 15:25 ` Andi Kleen
2021-04-14 14:10 ` Liuxiangdong
2021-04-14 14:49 ` Liuxiangdong
2021-04-15 1:38 ` Xu, Like
2021-04-15 2:49 ` Liuxiangdong
2021-04-15 3:23 ` Like Xu
2021-04-06 12:47 ` Andi Kleen
2021-04-07 3:05 ` Liuxiangdong (Aven, Cloud Infrastructure Service Product Dept.)
2021-04-07 14:32 ` Andi Kleen
2021-03-29 5:41 ` [PATCH v4 02/16] perf/x86/intel: Handle guest PEBS overflow PMI for KVM guest Like Xu
2021-04-06 16:22 ` Peter Zijlstra
2021-04-07 0:47 ` Xu, Like
2021-03-29 5:41 ` [PATCH v4 03/16] perf/x86/core: Pass "struct kvm_pmu *" to determine the guest values Like Xu
2021-03-29 5:41 ` [PATCH v4 04/16] KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled Like Xu
2021-03-29 5:41 ` [PATCH v4 05/16] KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter Like Xu
2021-03-29 5:41 ` [PATCH v4 06/16] KVM: x86/pmu: Reprogram guest PEBS event to emulate guest PEBS counter Like Xu
2021-04-07 8:40 ` Peter Zijlstra
2021-03-29 5:41 ` [PATCH v4 07/16] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS Like Xu
2021-04-07 8:56 ` Peter Zijlstra
2021-04-07 15:25 ` Peter Zijlstra
2021-03-29 5:41 ` [PATCH v4 08/16] KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to manage guest DS buffer Like Xu
2021-04-07 15:39 ` Peter Zijlstra
2021-04-08 5:39 ` Xu, Like [this message]
2021-04-08 7:52 ` Peter Zijlstra
2021-04-08 8:44 ` Xu, Like
2021-04-09 7:07 ` Xu, Like
2021-04-09 7:59 ` Peter Zijlstra
2021-04-09 8:30 ` Xu, Like
2021-03-29 5:41 ` [PATCH v4 09/16] KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation to support adaptive PEBS Like Xu
2021-04-07 15:40 ` Peter Zijlstra
2021-03-29 5:41 ` [PATCH v4 10/16] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled Like Xu
2021-03-29 5:41 ` [PATCH v4 11/16] KVM: x86/pmu: Adjust precise_ip to emulate Ice Lake guest PDIR counter Like Xu
2021-03-29 5:41 ` [PATCH v4 12/16] KVM: x86/pmu: Move pmc_speculative_in_use() to arch/x86/kvm/pmu.h Like Xu
2021-03-29 5:41 ` [PATCH v4 13/16] KVM: x86/pmu: Disable guest PEBS before vm-entry in two cases Like Xu
2021-03-29 5:41 ` [PATCH v4 14/16] KVM: x86/pmu: Add kvm_pmu_cap to optimize perf_get_x86_pmu_capability Like Xu
2021-03-29 5:41 ` [PATCH v4 15/16] KVM: x86/cpuid: Refactor host/guest CPU model consistency check Like Xu
2021-03-29 5:41 ` [PATCH v4 16/16] KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64 Like Xu
2021-04-06 3:19 ` [PATCH v4 00/16] KVM: x86/pmu: Add basic support to enable Guest PEBS via DS Xu, Like
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