From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755987AbdKCLCs (ORCPT ); Fri, 3 Nov 2017 07:02:48 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40834 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752719AbdKCLCq (ORCPT ); Fri, 3 Nov 2017 07:02:46 -0400 Subject: Re: [PATCH 4/8] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe To: Zhao Qiang , tglx@linutronix.de, jason@lakedaemon.net Cc: linux-kernel@vger.kernel.org References: <20171101013457.17365-1-qiang.zhao@nxp.com> <20171101013457.17365-4-qiang.zhao@nxp.com> From: Marc Zyngier Organization: ARM Ltd Message-ID: <620f99fb-248e-6531-f3e8-df6c5bf42ac9@arm.com> Date: Fri, 3 Nov 2017 11:02:43 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <20171101013457.17365-4-qiang.zhao@nxp.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/11/17 01:34, Zhao Qiang wrote: > move the driver from drivers/soc/fsl/qe to drivers/irqchip, > merge qe_ic.h and qe_ic.c into irq-qeic.c. > > Signed-off-by: Zhao Qiang > --- > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-qeic.c | 601 ++++++++++++++++++++++++++++++++++++++++++++ > drivers/soc/fsl/qe/Makefile | 2 +- > drivers/soc/fsl/qe/qe_ic.c | 512 ------------------------------------- > drivers/soc/fsl/qe/qe_ic.h | 103 -------- > 5 files changed, 603 insertions(+), 616 deletions(-) > create mode 100644 drivers/irqchip/irq-qeic.c > delete mode 100644 drivers/soc/fsl/qe/qe_ic.c > delete mode 100644 drivers/soc/fsl/qe/qe_ic.h So that's where this is hiding. Next time, please send one consistent series, not something that is spanned across two series with no indication of the dependency. > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > index 0e55d94..627c5d6 100644 > --- a/drivers/irqchip/Makefile > +++ b/drivers/irqchip/Makefile > @@ -75,3 +75,4 @@ obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o > obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o > obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o > obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o > +obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o > diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c > new file mode 100644 > index 0000000..48ceded > --- /dev/null > +++ b/drivers/irqchip/irq-qeic.c > @@ -0,0 +1,601 @@ > +/* > + * drivers/irqchip/irq-qeic.c > + * > + * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved. > + * > + * Author: Li Yang > + * Based on code from Shlomi Gridish > + * > + * QUICC ENGINE Interrupt Controller > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define NR_QE_IC_INTS 64 > + > +/* QE IC registers offset */ > +#define QEIC_CICR 0x00 > +#define QEIC_CIVEC 0x04 > +#define QEIC_CRIPNR 0x08 > +#define QEIC_CIPNR 0x0c > +#define QEIC_CIPXCC 0x10 > +#define QEIC_CIPYCC 0x14 > +#define QEIC_CIPWCC 0x18 > +#define QEIC_CIPZCC 0x1c > +#define QEIC_CIMR 0x20 > +#define QEIC_CRIMR 0x24 > +#define QEIC_CICNR 0x28 > +#define QEIC_CIPRTA 0x30 > +#define QEIC_CIPRTB 0x34 > +#define QEIC_CRICR 0x3c > +#define QEIC_CHIVEC 0x60 > + > +/* Interrupt priority registers */ > +#define CIPCC_SHIFT_PRI0 29 > +#define CIPCC_SHIFT_PRI1 26 > +#define CIPCC_SHIFT_PRI2 23 > +#define CIPCC_SHIFT_PRI3 20 > +#define CIPCC_SHIFT_PRI4 13 > +#define CIPCC_SHIFT_PRI5 10 > +#define CIPCC_SHIFT_PRI6 7 > +#define CIPCC_SHIFT_PRI7 4 > + > +/* CICR priority modes */ > +#define CICR_GWCC 0x00040000 > +#define CICR_GXCC 0x00020000 > +#define CICR_GYCC 0x00010000 > +#define CICR_GZCC 0x00080000 > +#define CICR_GRTA 0x00200000 > +#define CICR_GRTB 0x00400000 > +#define CICR_HPIT_SHIFT 8 > +#define CICR_HPIT_MASK 0x00000300 > +#define CICR_HP_SHIFT 24 > +#define CICR_HP_MASK 0x3f000000 > + > +/* CICNR */ > +#define CICNR_WCC1T_SHIFT 20 > +#define CICNR_ZCC1T_SHIFT 28 > +#define CICNR_YCC1T_SHIFT 12 > +#define CICNR_XCC1T_SHIFT 4 > + > +/* CRICR */ > +#define CRICR_RTA1T_SHIFT 20 > +#define CRICR_RTB1T_SHIFT 28 > + > +/* Signal indicator */ > +#define SIGNAL_MASK 3 > +#define SIGNAL_HIGH 2 > +#define SIGNAL_LOW 0 > + > +struct qe_ic { > + /* Control registers offset */ > + volatile u32 __iomem *regs; > + > + /* The remapper for this QEIC */ > + struct irq_domain *irqhost; > + > + /* The "linux" controller struct */ > + struct irq_chip hc_irq; > + > + /* VIRQ numbers of QE high/low irqs */ > + unsigned int virq_high; > + unsigned int virq_low; > +}; > + > +/* > + * QE interrupt controller internal structure > + */ > +struct qe_ic_info { > + /* location of this source at the QIMR register. */ > + u32 mask; > + > + /* Mask register offset */ > + u32 mask_reg; > + > + /* > + * for grouped interrupts sources - the interrupt > + * code as appears at the group priority register > + */ > + u8 pri_code; > + > + /* Group priority register offset */ > + u32 pri_reg; > +}; > + > +static DEFINE_RAW_SPINLOCK(qe_ic_lock); > + > +static struct qe_ic_info qe_ic_info[] = { > + [1] = { > + .mask = 0x00008000, Please write those single-bit constants as BIT(x), as it makes the code much more readable. M. -- Jazz is not dead. It just smells funny...