From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A508ECDFB3 for ; Tue, 17 Jul 2018 13:09:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B94E82145D for ; Tue, 17 Jul 2018 13:09:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B94E82145D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=st.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731566AbeGQNmb (ORCPT ); Tue, 17 Jul 2018 09:42:31 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:39568 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731464AbeGQNmb (ORCPT ); Tue, 17 Jul 2018 09:42:31 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w6HD9aiW015006; Tue, 17 Jul 2018 15:09:36 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2k87uegw1m-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 17 Jul 2018 15:09:36 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A4FD13D; Tue, 17 Jul 2018 13:09:34 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node1.st.com [10.75.127.16]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B66065406; Tue, 17 Jul 2018 13:09:34 +0000 (GMT) Received: from [10.48.0.237] (10.75.127.48) by SFHDAG6NODE1.st.com (10.75.127.16) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 17 Jul 2018 15:09:34 +0200 Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: add syscfg mask parameter To: Linus Walleij , Rob Herring CC: Maxime Coquelin , Alexandre Torgue , , , References: <1531821387-29845-1-git-send-email-ludovic.Barre@st.com> <1531821387-29845-2-git-send-email-ludovic.Barre@st.com> From: Ludovic BARRE Message-ID: <62475855-71e4-3fd1-8f92-28236fdc16fa@st.com> Date: Tue, 17 Jul 2018 15:09:33 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <1531821387-29845-2-git-send-email-ludovic.Barre@st.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG4NODE3.st.com (10.75.127.12) To SFHDAG6NODE1.st.com (10.75.127.16) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-07-17_03:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi add Rob, I forgotten rob's mail. On 07/17/2018 11:56 AM, Ludovic Barre wrote: > From: Ludovic Barre > > This patch adds mask parameter to define IRQ mux field. > This field could vary depend of IRQ mux selection register. > This parameter is needed if the mask is different of 0xf. > > Signed-off-by: Ludovic Barre > --- > Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt > index 9a06e1f..4d60119 100644 > --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt > @@ -39,9 +39,10 @@ Optional properties: > - reset: : Reference to the reset controller > - interrupt-parent: phandle of the interrupt parent to which the external > GPIO interrupts are forwarded to. > - - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node > - which includes IRQ mux selection register, and the offset of the IRQ mux > - selection register. > + - st,syscfg: Should be phandle/offset/mask. > + -The phandle to the syscon node which includes IRQ mux selection register. > + -The offset of the IRQ mux selection register > + -The field mask of IRQ mux, needed if different of 0xf. > - gpio-ranges: Define a dedicated mapping between a pin-controller and > a gpio controller. Format is <&phandle a b c> with: > -(phandle): phandle of pin-controller. >