From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA691C432BE for ; Fri, 23 Jul 2021 20:06:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B045360E98 for ; Fri, 23 Jul 2021 20:06:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231274AbhGWTZc (ORCPT ); Fri, 23 Jul 2021 15:25:32 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:61996 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231163AbhGWTZb (ORCPT ); Fri, 23 Jul 2021 15:25:31 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1627070764; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=R6B44KvNJoUb62PuGtXARkIntmCEbpuSvDX2oWLc0ew=; b=H9b7TkTPl020zMNI6Jhnbye4jSxR6uOlZ8uTtrt3Jl0KX/R30YheFSI3cNY/MLzwLaX/A3KF auImQXfha5xOQdwQ4sxgCmdJ0eoUrAZKLKiCv+kcmiNmCFiwNmjluNDEAgQF8fgigmURoxN4 ugMoRy6s4oDA/zUG8+MqBtTDcgY= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 60fb21144815712f3ad1d3f7 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 23 Jul 2021 20:05:40 GMT Sender: abhinavk=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 2A078C43143; Fri, 23 Jul 2021 20:05:40 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: abhinavk) by smtp.codeaurora.org (Postfix) with ESMTPSA id 179F8C433F1; Fri, 23 Jul 2021 20:05:39 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Fri, 23 Jul 2021 13:05:38 -0700 From: abhinavk@codeaurora.org To: Bjorn Andersson Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/5] dt-bindings: msm/dp: Change reg definition In-Reply-To: <20210722024227.3313096-2-bjorn.andersson@linaro.org> References: <20210722024227.3313096-1-bjorn.andersson@linaro.org> <20210722024227.3313096-2-bjorn.andersson@linaro.org> Message-ID: <6318d5abc7f1ed9622218bf29394ec64@codeaurora.org> X-Sender: abhinavk@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021-07-21 19:42, Bjorn Andersson wrote: > reg was defined as one region covering the entire DP block, but the > memory map is actually split in 4 regions and obviously the size of > these regions differs between platforms. > > Switch the reg to require that all four regions are specified instead. > It is expected that the implementation will handle existing DTBs, even > though the schema defines the new layout. > > Signed-off-by: Bjorn Andersson > --- > .../bindings/display/msm/dp-controller.yaml | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > index 64d8d9e5e47a..a6e41be038fc 100644 > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > @@ -19,7 +19,11 @@ properties: > - qcom,sc7180-dp > > reg: > - maxItems: 1 > + items: > + - description: ahb register block > + - description: aux register block > + - description: link register block > + - description: p0 register block Do you also want to add the p1 register block here? > > interrupts: > maxItems: 1 > @@ -100,7 +104,10 @@ examples: > > displayport-controller@ae90000 { > compatible = "qcom,sc7180-dp"; > - reg = <0xae90000 0x1400>; > + reg = <0xae90000 0x200>, > + <0xae90200 0x200>, > + <0xae90400 0xc00>, > + <0xae91000 0x400>; here too? > interrupt-parent = <&mdss>; > interrupts = <12>; > clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,