From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A2A7C64E90 for ; Mon, 30 Nov 2020 14:13:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9A4CA2085B for ; Mon, 30 Nov 2020 14:13:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="hW1W0YyK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727026AbgK3ON1 (ORCPT ); Mon, 30 Nov 2020 09:13:27 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:31529 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726314AbgK3ON0 (ORCPT ); Mon, 30 Nov 2020 09:13:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1606745519; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2zv6+ucodm/xfDYyg+Sh6U/WzFb0IF6DwZNXabv7t90=; b=hW1W0YyKj8J0RkRA7kw0VLsFGAKEnSx/zswUGRJcsVY4Ii8rFBjSrSnC3PDtVHSaQF31zE RNRlZ748/JK/FDCIcgwIJ8x6kj26D8ASLhAvY6akZalZuGV81fvAvpYzN0edlQcqmWIodm cD8TAz+tNnBptNjW8EJF1I0zbuzzzGc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-511-ZXWjAzGHO5eKzT-pFkIYUA-1; Mon, 30 Nov 2020 09:11:55 -0500 X-MC-Unique: ZXWjAzGHO5eKzT-pFkIYUA-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 098EF807357; Mon, 30 Nov 2020 14:11:53 +0000 (UTC) Received: from starship (unknown [10.35.206.90]) by smtp.corp.redhat.com (Postfix) with ESMTP id AFB0063B8C; Mon, 30 Nov 2020 14:11:45 +0000 (UTC) Message-ID: <638a2919cf7c11c55108776beecafdd8e2da2995.camel@redhat.com> Subject: Re: [PATCH 2/2] KVM: x86: introduce KVM_X86_QUIRK_TSC_HOST_ACCESS From: Maxim Levitsky To: Paolo Bonzini , kvm@vger.kernel.org Cc: Oliver Upton , Ingo Molnar , Sean Christopherson , Thomas Gleixner , open list , Marcelo Tosatti , Jonathan Corbet , Wanpeng Li , Borislav Petkov , Jim Mattson , "H. Peter Anvin" , "open list:DOCUMENTATION" , Joerg Roedel , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , Vitaly Kuznetsov Date: Mon, 30 Nov 2020 16:11:43 +0200 In-Reply-To: References: <20201130133559.233242-1-mlevitsk@redhat.com> <20201130133559.233242-3-mlevitsk@redhat.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.36.3 (3.36.3-1.fc32) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2020-11-30 at 14:54 +0100, Paolo Bonzini wrote: > On 30/11/20 14:35, Maxim Levitsky wrote: > > This quirk reflects the fact that we currently treat MSR_IA32_TSC > > and MSR_TSC_ADJUST access by the host (e.g qemu) in a way that is different > > compared to an access from the guest. > > > > For host's MSR_IA32_TSC read we currently always return L1 TSC value, and for > > host's write we do the tsc synchronization. > > > > For host's MSR_TSC_ADJUST write, we don't make the tsc 'jump' as we should > > for this msr. > > > > When the hypervisor uses the new TSC GET/SET state ioctls, all of this is no > > longer needed, thus leave this enabled only with a quirk > > which the hypervisor can disable. > > > > Suggested-by: Paolo Bonzini > > Signed-off-by: Maxim Levitsky > > This needs to be covered by a variant of the existing selftests testcase > (running the same guest code, but different host code of course). Do you think that the test should go to the kernel's kvm unit tests, or to kvm-unit-tests project? Best regards, Maxim Levitsky > > Paolo > > > --- > > arch/x86/include/uapi/asm/kvm.h | 1 + > > arch/x86/kvm/x86.c | 19 ++++++++++++++----- > > 2 files changed, 15 insertions(+), 5 deletions(-) > > > > diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h > > index 8e76d3701db3f..2a60fc6674164 100644 > > --- a/arch/x86/include/uapi/asm/kvm.h > > +++ b/arch/x86/include/uapi/asm/kvm.h > > @@ -404,6 +404,7 @@ struct kvm_sync_regs { > > #define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) > > #define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) > > #define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) > > +#define KVM_X86_QUIRK_TSC_HOST_ACCESS (1 << 5) > > > > #define KVM_STATE_NESTED_FORMAT_VMX 0 > > #define KVM_STATE_NESTED_FORMAT_SVM 1 > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > > index 4f0ae9cb14b8a..46a2111d54840 100644 > > --- a/arch/x86/kvm/x86.c > > +++ b/arch/x86/kvm/x86.c > > @@ -3091,7 +3091,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > > break; > > case MSR_IA32_TSC_ADJUST: > > if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { > > - if (!msr_info->host_initiated) { > > + if (!msr_info->host_initiated || > > + !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_TSC_HOST_ACCESS)) { > > s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; > > adjust_tsc_offset_guest(vcpu, adj); > > } > > @@ -3118,7 +3119,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > > vcpu->arch.msr_ia32_power_ctl = data; > > break; > > case MSR_IA32_TSC: > > - if (msr_info->host_initiated) { > > + if (msr_info->host_initiated && > > + kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_TSC_HOST_ACCESS)) { > > kvm_synchronize_tsc(vcpu, data); > > } else { > > u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; > > @@ -3409,17 +3411,24 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > > msr_info->data = vcpu->arch.msr_ia32_power_ctl; > > break; > > case MSR_IA32_TSC: { > > + u64 tsc_offset; > > + > > /* > > * Intel SDM states that MSR_IA32_TSC read adds the TSC offset > > * even when not intercepted. AMD manual doesn't explicitly > > * state this but appears to behave the same. > > * > > - * On userspace reads and writes, however, we unconditionally > > + * On userspace reads and writes, when KVM_X86_QUIRK_SPECIAL_TSC_READ > > + * is present, however, we unconditionally > > * return L1's TSC value to ensure backwards-compatible > > * behavior for migration. > > */ > > - u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : > > - vcpu->arch.tsc_offset; > > + > > + if (msr_info->host_initiated && > > + kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_TSC_HOST_ACCESS)) > > + tsc_offset = vcpu->arch.l1_tsc_offset; > > + else > > + tsc_offset = vcpu->arch.tsc_offset; > > > > msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; > > break; > >