From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0711AC5B578 for ; Mon, 8 Jul 2019 07:58:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D26AB20879 for ; Mon, 8 Jul 2019 07:58:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728286AbfGHH62 (ORCPT ); Mon, 8 Jul 2019 03:58:28 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54996 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725836AbfGHH60 (ORCPT ); Mon, 8 Jul 2019 03:58:26 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 349E35AFE3; Mon, 8 Jul 2019 07:58:26 +0000 (UTC) Received: from [10.36.116.46] (ovpn-116-46.ams2.redhat.com [10.36.116.46]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 936D818ACB; Mon, 8 Jul 2019 07:58:23 +0000 (UTC) Subject: Re: [PATCH 3/8] iommu/arm-smmu-v3: Support platform SSID To: Jean-Philippe Brucker , will.deacon@arm.com Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, robin.murphy@arm.com, jacob.jun.pan@linux.intel.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20190610184714.6786-1-jean-philippe.brucker@arm.com> <20190610184714.6786-4-jean-philippe.brucker@arm.com> From: Auger Eric Message-ID: <63d4a71a-8e3f-f663-34bc-6647971b7e4b@redhat.com> Date: Mon, 8 Jul 2019 09:58:22 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20190610184714.6786-4-jean-philippe.brucker@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Mon, 08 Jul 2019 07:58:26 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jean, On 6/10/19 8:47 PM, Jean-Philippe Brucker wrote: > For platform devices that support SubstreamID (SSID), firmware provides > the number of supported SSID bits. Restrict it to what the SMMU supports > and cache it into master->ssid_bits. The commit message may give the impression the master's ssid_bits field only is used for platform devices. > > Signed-off-by: Jean-Philippe Brucker > --- > drivers/iommu/arm-smmu-v3.c | 11 +++++++++++ > drivers/iommu/of_iommu.c | 6 +++++- > include/linux/iommu.h | 1 + > 3 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > index 4d5a694f02c2..3254f473e681 100644 > --- a/drivers/iommu/arm-smmu-v3.c > +++ b/drivers/iommu/arm-smmu-v3.c > @@ -604,6 +604,7 @@ struct arm_smmu_master { > struct list_head domain_head; > u32 *sids; > unsigned int num_sids; > + unsigned int ssid_bits; > bool ats_enabled :1; > }; > > @@ -2097,6 +2098,16 @@ static int arm_smmu_add_device(struct device *dev) > } > } > > + master->ssid_bits = min(smmu->ssid_bits, fwspec->num_pasid_bits); In case the device is a PCI device, what is the value taken by fwspec->num_pasid_bits? > + > + /* > + * If the SMMU doesn't support 2-stage CD, limit the linear > + * tables to a reasonable number of contexts, let's say > + * 64kB / sizeof(ctx_desc) = 1024 = 2^10 ctx_desc is 26B so 11bits would be OK > + */ > + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) > + master->ssid_bits = min(master->ssid_bits, 10U); > + > group = iommu_group_get_for_dev(dev); > if (!IS_ERR(group)) { > iommu_group_put(group); > diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c > index f04a6df65eb8..04f4f6b95d82 100644 > --- a/drivers/iommu/of_iommu.c > +++ b/drivers/iommu/of_iommu.c > @@ -206,8 +206,12 @@ const struct iommu_ops *of_iommu_configure(struct device *dev, > if (err) > break; > } > - } > > + fwspec = dev_iommu_fwspec_get(dev); > + if (!err && fwspec) > + of_property_read_u32(master_np, "pasid-num-bits", > + &fwspec->num_pasid_bits); > + } > > /* > * Two success conditions can be represented by non-negative err here: > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > index 519e40fb23ce..b91df613385f 100644 > --- a/include/linux/iommu.h > +++ b/include/linux/iommu.h > @@ -536,6 +536,7 @@ struct iommu_fwspec { > struct fwnode_handle *iommu_fwnode; > void *iommu_priv; > u32 flags; > + u32 num_pasid_bits; > unsigned int num_ids; > u32 ids[1]; > }; > Thanks Eric