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[24.205.208.113]) by smtp.gmail.com with ESMTPSA id q7-20020a9d6647000000b005af185bf273sm1582024otm.25.2022.03.03.14.04.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Mar 2022 14:04:02 -0800 (PST) Subject: Re: [PATCH v2 1/2] Documentation: fpga: dfl: add PCI Identification documentation To: matthew.gerlach@linux.intel.com, hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, mdf@kernel.org, corbet@lwn.net, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, dan.j.williams@intel.com, ashok.raj@intel.com, tianfei.zhang@intel.com References: <20220303003534.3307971-1-matthew.gerlach@linux.intel.com> <20220303003534.3307971-2-matthew.gerlach@linux.intel.com> From: Tom Rix Message-ID: <6448f21f-7ce1-d9ce-1048-29aca14f9d3d@redhat.com> Date: Thu, 3 Mar 2022 14:04:00 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <20220303003534.3307971-2-matthew.gerlach@linux.intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/2/22 4:35 PM, matthew.gerlach@linux.intel.com wrote: > From: Matthew Gerlach > > Add documentation on identifying FPGA based PCI cards prompted > by discussion on the linux-fpga@vger.kernel.org mailing list. > > Signed-off-by: Matthew Gerlach > --- > v2: Introduced in v2. > --- > Documentation/fpga/dfl.rst | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > index ef9eec71f6f3..5fb2ca8e76d7 100644 > --- a/Documentation/fpga/dfl.rst > +++ b/Documentation/fpga/dfl.rst > @@ -502,6 +502,26 @@ Developer only needs to provide a sub feature driver with matched feature id. > FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) > could be a reference. > > +PCI Device Identification > +================================ > +Since FPGA based PCI cards can be reconfigured to a perform a completely > +new function at runtime, properly identifying such cards and binding the > +correct driver can be challenging. In many use cases, deployed FPGA based > +PCI cards are essentially static and the PCI Product ID and Vendor ID pair > +is sufficient to identify the card. The DFL framework helps with the > +dynamic case of deployed FPGA cards changing at run time by providing > +more detailed information about card discoverable at runtime. > + > +At one level, the DFL on a PCI card describes the function of the card. > +However, the same DFL could be instantiated on different physical cards. > +Conversely, different DFLs could be instantiated on the same physical card. > +Practical management of a cloud containing a heterogeneous set of such cards > +requires a PCI level of card identification. While the PCI Product ID and > +Vendor ID may be sufficient to bind the dfl-pci driver, it is expected > +that FPGA PCI cards would advertise suitable Subsystem ID and Subsystem > +Vendor ID values. PCI Vital Product Data (VPD) can also be used for > +more granular information about the board. This describes a bit more of the problem, it should describe it wrt ofs dev id. The introduction of the ofs dev should be explicitly called out as a generic pci id. Why couldn't one of the old pci id's be reused ? How will the subvendor/subid be enforced ? Is the current security manager patchset smart enough to save the board from being bricked when a user doesn't look beyond the pci id ? What happens if a board uses this device id but doesn't have a max10 to do the update ? Tom > + > Location of DFLs on a PCI Device > ================================ > The original method for finding a DFL on a PCI device assumed the start of the