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([2a01:e34:ed2f:f020:c9b2:a9e9:8b67:65fc]) by smtp.googlemail.com with ESMTPSA id g17sm11125539wrw.31.2021.06.28.13.42.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Jun 2021 13:42:05 -0700 (PDT) Subject: Re: [PATCH] thermal: int340x: processor_thermal: Fix tcc setting To: Srinivas Pandruvada , rui.zhang@intel.com, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20210628201012.68642-1-srinivas.pandruvada@linux.intel.com> From: Daniel Lezcano Message-ID: <649bc24b-331d-9ffd-e374-18eed5555816@linaro.org> Date: Mon, 28 Jun 2021 22:42:04 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210628201012.68642-1-srinivas.pandruvada@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28/06/2021 22:10, Srinivas Pandruvada wrote: > The following fixes are done for tcc sysfs interface: > - TCC is 6 bits only from bit 29-24 > - TCC of 0 is valid > - When BIT(31) is set, this register is read only > - Check for invalid tcc value > - Error for negative values > Fixes: fdf4f2fb8e899 ("Export sysfs interface for TCC") ? > Signed-off-by: Srinivas Pandruvada > --- > .../processor_thermal_device.c | 20 +++++++++++-------- > 1 file changed, 12 insertions(+), 8 deletions(-) > > diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c b/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c > index de4fc640deb0..0f0038af2ad4 100644 > --- a/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c > +++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c > @@ -78,24 +78,27 @@ static ssize_t tcc_offset_degree_celsius_show(struct device *dev, > if (err) > return err; > > - val = (val >> 24) & 0xff; > + val = (val >> 24) & 0x3f; > return sprintf(buf, "%d\n", (int)val); > } > > -static int tcc_offset_update(int tcc) > +static int tcc_offset_update(unsigned int tcc) > { > u64 val; > int err; > > - if (!tcc) > + if (tcc > 63) > return -EINVAL; > > err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); > if (err) > return err; > > - val &= ~GENMASK_ULL(31, 24); > - val |= (tcc & 0xff) << 24; > + if (val & BIT(31)) > + return -EPERM; > + > + val &= ~GENMASK_ULL(29, 24); > + val |= (tcc & 0x3f) << 24; > > err = wrmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, val); > if (err) > @@ -104,14 +107,15 @@ static int tcc_offset_update(int tcc) > return 0; > } > > -static int tcc_offset_save; > +static unsigned int tcc_offset_save; > > static ssize_t tcc_offset_degree_celsius_store(struct device *dev, > struct device_attribute *attr, const char *buf, > size_t count) > { > + unsigned int tcc; > u64 val; > - int tcc, err; > + int err; > > err = rdmsrl_safe(MSR_PLATFORM_INFO, &val); > if (err) > @@ -120,7 +124,7 @@ static ssize_t tcc_offset_degree_celsius_store(struct device *dev, > if (!(val & BIT(30))) > return -EACCES; > > - if (kstrtoint(buf, 0, &tcc)) > + if (kstrtouint(buf, 0, &tcc)) > return -EINVAL; > > err = tcc_offset_update(tcc); > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog