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From: Dave Hansen <dave.hansen@intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
	Reinette Chatre <reinette.chatre@intel.com>
Cc: tglx@linutronix.de, mingo@redhat.com, fenghua.yu@intel.com,
	tony.luck@intel.com, vikas.shivappa@linux.intel.com,
	gavin.hindman@intel.com, jithu.joseph@intel.com, hpa@zytor.com,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination with perf
Date: Thu, 2 Aug 2018 11:18:01 -0700	[thread overview]
Message-ID: <653e874f-5e77-a9b5-996a-ed9daa3c6d43@intel.com> (raw)
In-Reply-To: <20180802173727.GP2494@hirez.programming.kicks-ass.net>

On 08/02/2018 10:37 AM, Peter Zijlstra wrote:
>> I do not see how I can do so without incurring the cache hits and misses
>> from the data needed and instructions run by this interface. Could you
>> please share how I can do so and still obtain the accurate measurement
>> of cache residency of a specific memory region?
> That's the best you're going to get. You do _NOT_ get to use raw PMU.

Hi Peter,

This code is really fidgety.  It's really easily perturbed even by tiny
things like implicit cache accesses from the page walker filling the TLB
from the page tables.

Adding a bunch more code in the way is surely going to make it more
fragile and imprecise.

I totally understand not wanting to fill the tree with code hijacking
the raw PMU.  Is your reaction to this really around not wanting to
start down the slippery slope that ends up with lots of raw PMU "owners"?

  reply	other threads:[~2018-08-02 18:18 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-31 19:38 [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination with perf Reinette Chatre
2018-07-31 19:38 ` [PATCH 1/2] perf/x86: Expose PMC hardware reservation Reinette Chatre
2018-07-31 19:38 ` [PATCH 2/2] x86/intel_rdt: Coordinate performance monitoring with perf Reinette Chatre
2018-08-02 12:39 ` [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination " Peter Zijlstra
2018-08-02 16:14   ` Reinette Chatre
2018-08-02 16:18     ` Peter Zijlstra
2018-08-02 16:44       ` Reinette Chatre
2018-08-02 17:37         ` Peter Zijlstra
2018-08-02 18:18           ` Dave Hansen [this message]
2018-08-02 19:54             ` Peter Zijlstra
2018-08-02 20:06               ` Dave Hansen
2018-08-02 20:13                 ` Peter Zijlstra
2018-08-02 20:43                   ` Reinette Chatre
2018-08-03 10:49                     ` Peter Zijlstra
2018-08-03 15:18                       ` Reinette Chatre
2018-08-03 15:25                         ` Peter Zijlstra
2018-08-03 18:37                           ` Reinette Chatre
2018-08-06 19:50                             ` Reinette Chatre
2018-08-06 22:12                               ` Peter Zijlstra
2018-08-06 23:07                                 ` Reinette Chatre
2018-08-07  9:36                                   ` Peter Zijlstra
     [not found]                                     ` <ace0bebb-91ab-5d40-e7d7-d72d48302fa8@intel.com>
2018-08-08  1:28                                       ` Luck, Tony
2018-08-08  5:44                                         ` Reinette Chatre
2018-08-08  7:41                                           ` Peter Zijlstra
2018-08-08 15:55                                             ` Luck, Tony
2018-08-08 16:47                                               ` Peter Zijlstra
2018-08-08 16:51                                                 ` Reinette Chatre
2018-08-08  7:51                                       ` Peter Zijlstra
2018-08-08 17:33                                         ` Reinette Chatre
2018-08-10 16:25                                           ` Reinette Chatre
2018-08-10 17:52                                             ` Reinette Chatre

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