From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x227Lmrhd8UCDM2dQp07EYq/62edY6kqAOSdJwozlUpY1fD3UaD90YPL2AC7e5mHxGL13JGA6 ARC-Seal: i=1; a=rsa-sha256; t=1516404444; cv=none; d=google.com; s=arc-20160816; b=ey6xCOOyENppNPzUw454kcNTKFZAV2vSNR6Fljn4sMx4zqfuXLiwqsoddsEmqVXUuz 4ZY6AkG9tbN9RB3/mcJ732lTUaIfma6F+Fs+67T+mYuRRyWiVdSWsBezrYwWNXSOriu6 ieYA5ovDISoGrWXY2tm4W4nLlpb5YmbQRD3Z3DQjCEpdl4a8z/pQ8s6YALQasgdpSgDO VZeHlJIidIuKdW/dKqGzGEwwJHpu1iQAU2jOyOuEzC3XIlWRWZvQqzXDIQvXRj3OPLrI gbEXTFkjl18ifWNw25qP4zEEs2K9z10HvB5WC4CGb+Z5RtA3n0Z3O1NuXcFlWZPqGbVP G1cQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:content-language:in-reply-to:mime-version :user-agent:date:message-id:from:references:cc:to:subject :arc-authentication-results; bh=eqng5fHHx5SLI/j72357qciwGtMhyNttJf2JQCo/RB4=; b=JNJTGpAnlFoeMC7RwnWVUkOcX/H6eCNOQATE9tT095pOCml0QXyn9gNTN4/Mlnd+sb 6feveYwzBMAH8BPK9Bt2ubRGvPCr76TeqgIYdJEwFY2iLd0C9t8pAnMuyS0EbKbeK5na jZCsB7xFLn/TOHZKx/+BjMRBUBXl5HtDnTLuBpbMmxih6ICegJpt3xz6Gp93q4oiJHP+ zqzDT0A8ctLB79kZCFLe09zJXEoAQPCf76RzKoYn32lrzJI8fYBVYVaNRdoyMJGOsE+B ZWkknKxayk0mlu8MV4w3oomIE0ZkW5f79EIGvV6oKH7YARL5X7q49oXW4N0p/F+XsupX kQEw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of jeremy.linton@arm.com designates 217.140.101.70 as permitted sender) smtp.mailfrom=jeremy.linton@arm.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of jeremy.linton@arm.com designates 217.140.101.70 as permitted sender) smtp.mailfrom=jeremy.linton@arm.com Subject: Re: [PATCH v6 02/12] drivers: base: cacheinfo: setup DT cache properties early To: Sudeep Holla Cc: linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, vkilari@codeaurora.org, morten.rasmussen@arm.com, Palmer Dabbelt , Albert Ou References: <20180113005920.28658-1-jeremy.linton@arm.com> <20180113005920.28658-3-jeremy.linton@arm.com> <20180115123338.GB5473@e107155-lin> <65f78c99-8b86-0098-7ced-899840a4bf16@arm.com> <15884ccc-2cfb-da91-5844-369d8237175d@arm.com> <05a8b375-70c4-34d4-6cde-8dd4cd62c10b@arm.com> From: Jeremy Linton Message-ID: <6627a9ef-8d62-3cdf-dbea-390770991f30@arm.com> Date: Fri, 19 Jan 2018 17:27:21 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <05a8b375-70c4-34d4-6cde-8dd4cd62c10b@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1589436997037379564?= X-GMAIL-MSGID: =?utf-8?q?1590065306892101114?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Hi, On 01/18/2018 04:14 AM, Sudeep Holla wrote: > > > On 17/01/18 18:51, Jeremy Linton wrote: >> Hi, >> >> On 01/17/2018 12:20 PM, Sudeep Holla wrote: >>> >>> >>> On 16/01/18 21:07, Jeremy Linton wrote: >>>> Hi, >>>> >>>> On 01/15/2018 06:33 AM, Sudeep Holla wrote: >>>>> On Fri, Jan 12, 2018 at 06:59:10PM -0600, Jeremy Linton wrote: >>>>>> The original intent in cacheinfo was that an architecture >>>>>> specific populate_cache_leaves() would probe the hardware >>>>>> and then cache_shared_cpu_map_setup() and >>>>>> cache_override_properties() would provide firmware help to >>>>>> extend/expand upon what was probed. Arm64 was really >>>>>> the only architecture that was working this way, and >>>>>> with the removal of most of the hardware probing logic it >>>>>> became clear that it was possible to simplify the logic a bit. >>>>>> >>>>>> This patch combines the walk of the DT nodes with the >>>>>> code updating the cache size/line_size and nr_sets. >>>>>> cache_override_properties() (which was DT specific) is >>>>>> then removed. The result is that cacheinfo.of_node is >>>>>> no longer used as a temporary place to hold DT references >>>>>> for future calls that update cache properties. That change >>>>>> helps to clarify its one remaining use (matching >>>>>> cacheinfo nodes that represent shared caches) which >>>>>> will be used by the ACPI/PPTT code in the following patches. >>>>>> >>>>>> Cc: Palmer Dabbelt >>>>>> Cc: Albert Ou >>>>>> Signed-off-by: Jeremy Linton >>>>>> --- >>>>>>    arch/riscv/kernel/cacheinfo.c |  1 + >>>>>>    drivers/base/cacheinfo.c      | 65 >>>>>> +++++++++++++++++++------------------------ >>>>>>    include/linux/cacheinfo.h     |  1 + >>>>>>    3 files changed, 31 insertions(+), 36 deletions(-) >>>>>> >>>>>> diff --git a/arch/riscv/kernel/cacheinfo.c >>>>>> b/arch/riscv/kernel/cacheinfo.c >>>>>> index 10ed2749e246..6f4500233cf8 100644 >>>>>> --- a/arch/riscv/kernel/cacheinfo.c >>>>>> +++ b/arch/riscv/kernel/cacheinfo.c >>>>>> @@ -30,6 +30,7 @@ static void ci_leaf_init(struct cacheinfo >>>>>> *this_leaf, >>>>>>            CACHE_WRITE_BACK >>>>>>            | CACHE_READ_ALLOCATE >>>>>>            | CACHE_WRITE_ALLOCATE; >>>>>> +    cache_of_set_props(this_leaf, node); >>>>> >>>>> This may be necessary but can it be done as later patch ? So far >>>>> nothing >>>>> is added that may break riscv IIUC. >>>> >>>> Well I think you have a bisection issue where the additional information >>>> will disappear between this patch and wherever we put this code back in. >>>> >>> >>> Hmm, I am sorry but I fail to see the issue. Before this change, >>> populate_cache_leaves just populated the info as per ci_leaf_init in >>> arch/riscv/kernel/cacheinfo.c and cache_override_properties used to fill >>> the remaining. >>> >>> After this patch, the same is achieved in cache_shared_cpu_map_setup. >>> >>> In both case, it was by the end of detect_cache_attributes, so I see no >>> issue. >>> >> >> >> Hi, >> >> I must be misunderstanding something. >> > > Looks like I was missing to understand something :) > >> AFAIK, The code in cache_setup_of_node() won't call cache_of_set_props() >> because it returns when there is an existing of_node (fw_unique) created >> by the riscv populate_cache_leaves(). That's why I'm making the direct >> call here. If we fail to get that change in place before >> cache_override_properties() is removed then the fields not set by the >> riscv code (size/etc) will be missing. > > Indeed. I am trying to avoid use of cache_of_set_props outside. > How about skipping setting up of fw_unique in ci_leaf_init instead ? > I've been thinking about this, but I'm hesitant because I don't have a good test platform for this code. Plus, I'm not 100% sure that the results are the same (is it possible that the platform setup node isn't the same as the one the the common code would find?). I also think I'm getting a little off topic with these patches in relation to what the core goal is (adding PPTT parsing).