From: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
To: bhelgaas@google.com, lorenzo.pieralisi@arm.com,
Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com,
robh+dt@kernel.org, mark.rutland@arm.com
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com
Subject: [PATCH v8 6/9] PCI: dwc: Define maximum number of vectors
Date: Fri, 27 Apr 2018 13:00:01 +0100 [thread overview]
Message-ID: <66e6e2a103c576a9e7f65a416b452e9c3e782de3.1524829928.git.gustavo.pimentel@synopsys.com> (raw)
In-Reply-To: <cover.1524829928.git.gustavo.pimentel@synopsys.com>
In-Reply-To: <cover.1524829928.git.gustavo.pimentel@synopsys.com>
Add a callback to define the maximum number of vectors used by the RC.
Since this is a parameter associated to each SoC IP setting, makes sense
to be configurable and easily visible to future modifications.
Set DesignWare driver vectors number maximum to 256.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Changes v3->v4:
- Nothing changed, just to follow the patch set version.
Changes v4->v5:
- Nothing changed, just to follow the patch set version.
Changes v5->v6:
- Nothing changed, just to follow the patch set version.
Changes v6->v7:
- Nothing changed, just to follow the patch set version.
Changes v7->v8:
- Patch description rework for an imperative verbal mode.
drivers/pci/dwc/pcie-designware-plat.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c
index efc315c..5937fed 100644
--- a/drivers/pci/dwc/pcie-designware-plat.c
+++ b/drivers/pci/dwc/pcie-designware-plat.c
@@ -48,8 +48,14 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp)
return 0;
}
+static void dw_plat_set_num_vectors(struct pcie_port *pp)
+{
+ pp->num_vectors = MAX_MSI_IRQS;
+}
+
static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
.host_init = dw_plat_pcie_host_init,
+ .set_num_vectors = dw_plat_set_num_vectors,
};
static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
--
2.7.4
next prev parent reply other threads:[~2018-04-27 12:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-27 11:59 [PATCH v8 0/9] DesignWare EP support and code clean up Gustavo Pimentel
2018-04-27 11:59 ` [PATCH v8 1/9] bindings: PCI: designware: Example update Gustavo Pimentel
2018-04-27 11:59 ` [PATCH v8 2/9] PCI: dwc: Add support for EP mode Gustavo Pimentel
2018-04-27 11:59 ` [PATCH v8 3/9] PCI: endpoint: functions/pci-epf-test: Add second entry Gustavo Pimentel
2018-04-30 14:22 ` Lorenzo Pieralisi
2018-04-30 16:36 ` Gustavo Pimentel
2018-04-27 11:59 ` [PATCH v8 4/9] bindings: PCI: designware: Add support for EP in DesignWare driver Gustavo Pimentel
2018-04-27 12:00 ` [PATCH v8 5/9] misc: pci_endpoint_test: Add DesignWare EP entry Gustavo Pimentel
2018-04-27 12:00 ` Gustavo Pimentel [this message]
2018-04-27 12:00 ` [PATCH v8 7/9] PCI: dwc: Replace lower into upper case characters Gustavo Pimentel
2018-04-27 12:00 ` [PATCH v8 8/9] PCI: dwc: Small computation improvement Gustavo Pimentel
2018-04-27 12:00 ` [PATCH v8 9/9] PCI: dwc: Replace magic number by defines Gustavo Pimentel
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