From: Michal Simek <michal.simek@xilinx.com>
To: linux-kernel@vger.kernel.org, monstr@monstr.eu,
michal.simek@xilinx.com, git@xilinx.com,
bharat.kumar.gogada@xilinx.com, kw@linux.com
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-pci@vger.kernel.org
Subject: [PATCH v3 1/2] dt-bindings: pci: xilinx-nwl: Document optional clock property
Date: Fri, 25 Jun 2021 12:48:22 +0200 [thread overview]
Message-ID: <67aa2c189337181bb2d7721fb616db5640587d2a.1624618100.git.michal.simek@xilinx.com> (raw)
In-Reply-To: <cover.1624618100.git.michal.simek@xilinx.com>
Clock property hasn't been documented in binding document but it is used
for quite a long time where clock was specified by commit 9c8a47b484ed
("arm64: dts: xilinx: Add the clock nodes for zynqmp").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
(no changes since v2)
Changes in v2:
- new patch in this series because I found that it has never been sent
Bharat: Can you please start to work on converting it to yaml?
---
Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
index 2d677e90a7e2..f56f8c58c5d9 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
@@ -35,6 +35,7 @@ Required properties:
Optional properties:
- dma-coherent: present if DMA operations are coherent
+- clocks: Input clock specifier. Refer to common clock bindings
Example:
++++++++
--
2.32.0
next prev parent reply other threads:[~2021-06-25 10:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-25 10:48 [PATCH v3 0/2] PCI: xilinx-nwl: Add clock handling Michal Simek
2021-06-25 10:48 ` Michal Simek [this message]
2021-07-14 19:47 ` [PATCH v3 1/2] dt-bindings: pci: xilinx-nwl: Document optional clock property Rob Herring
2021-06-25 10:48 ` [PATCH v3 2/2] PCI: xilinx-nwl: Enable the clock through CCF Michal Simek
2021-08-06 10:28 ` [PATCH v3 0/2] PCI: xilinx-nwl: Add clock handling Michal Simek
2021-08-13 14:40 ` Lorenzo Pieralisi
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