From: Marc Zyngier <firstname.lastname@example.org> To: John Garry <email@example.com> Cc: Ming Lei <firstname.lastname@example.org>, <email@example.com>, "chenxiang (M)" <firstname.lastname@example.org>, <email@example.com>, <firstname.lastname@example.org>, <email@example.com>, <firstname.lastname@example.org>, <email@example.com>, <firstname.lastname@example.org>, <email@example.com>, <firstname.lastname@example.org> Subject: Re: [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity for managed interrupt Date: Mon, 16 Dec 2019 18:00:11 +0000 Message-ID: <email@example.com> (raw) In-Reply-To: <firstname.lastname@example.org> Hi John, On 2019-12-16 14:17, John Garry wrote: > Hi Marc, > >>> >>> I'm just wondering if non-managed interrupts should be included in >>> the load balancing calculation? Couldn't irqbalance (if active) >>> start >>> moving non-managed interrupts around anyway? >> But they are, aren't they? See what we do in irq_set_affinity: >> + atomic_inc(per_cpu_ptr(&cpu_lpi_count, cpu)); >> + atomic_dec(per_cpu_ptr(&cpu_lpi_count, >> + its_dev->event_map.col_map[id])); >> We don't try to "rebalance" anything based on that though, not that >> I think we should. > > Ah sorry, I meant whether they should not be included. In > its_irq_domain_activate(), we increment the per-cpu lpi count and > also > use its_pick_target_cpu() to find the least loaded cpu. I am asking > whether we should just stick with the old policy for non-managed > interrupts here. > > After checking D05, I see a very significant performance hit for SAS > controller performance - ~40% throughout lowering. -ETOOMANYMOVINGPARTS. > With this patch, now we have effective affinity targeted at seemingly > "random" CPUs, as opposed to all just using CPU0. This affects > performance. And piling all interrupts on the same CPU does help? > The difference is that when we use managed interrupts - like for NVME > or D06 SAS controller - the irq cpu affinity mask matches the CPUs > which enqueue the requests to the queue associated with the > interrupt. > So there is an efficiency is enqueuing and deqeueing on same CPU > group > - all related to blk multi-queue. And this is not the case for > non-managed interrupts. So you enqueue requests from CPU0 only? It seems a bit odd... >>>> Please give this new patch a shot on your system (my D05 doesn't >>>> have >>>> any managed devices): >>> >>> We could consider supporting platform msi managed interrupts, but I >>> doubt the value. >> It shouldn't be hard to do, and most of the existing code could be >> moved to the generic level. As for the value, I'm not convinced >> either. For example D05 uses the MBIGEN as an intermediate interrupt >> controller, so MSIs are from the PoV of MBIGEN, and not the SAS >> device >> attached to it. Not the best design... > > JFYI, I did raise this following topic before, but that's as far as I > got: > > https://marc.info/?l=linux-block&m=150722088314310&w=2 Yes. And that's probably not very hard, but the problem in your case is that the D05 HW is not using MSIs... You'd have to provide an abstraction for wired interrupts (please don't). You'd be better off directly setting the affinity of the interrupts from the driver, but I somehow can't believe that you're only submitting requests from the same CPU, always. There must be something I'm missing. Thanks, M. -- Jazz is not dead. It just smells funny...
next prev parent reply index Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-06 14:35 [PATCH RFC 0/1] Threaded handler uses irq affinity for when the interrupt is managed John Garry 2019-12-06 14:35 ` [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity for managed interrupt John Garry 2019-12-06 15:22 ` Marc Zyngier 2019-12-06 16:16 ` John Garry 2019-12-07 8:03 ` Ming Lei 2019-12-09 14:30 ` John Garry 2019-12-09 15:09 ` Hannes Reinecke 2019-12-09 15:17 ` Marc Zyngier 2019-12-09 15:25 ` Hannes Reinecke 2019-12-09 15:36 ` Marc Zyngier 2019-12-09 15:49 ` Qais Yousef 2019-12-09 15:55 ` Marc Zyngier 2019-12-10 1:43 ` Ming Lei 2019-12-10 9:45 ` John Garry 2019-12-10 10:06 ` Ming Lei 2019-12-10 10:28 ` Marc Zyngier 2019-12-10 10:59 ` John Garry 2019-12-10 11:36 ` Marc Zyngier 2019-12-10 12:05 ` John Garry 2019-12-10 18:32 ` Marc Zyngier 2019-12-11 9:41 ` John Garry 2019-12-13 10:07 ` John Garry 2019-12-13 10:31 ` Marc Zyngier 2019-12-13 12:08 ` John Garry 2019-12-14 10:59 ` Marc Zyngier 2019-12-11 17:09 ` John Garry 2019-12-12 22:38 ` Ming Lei 2019-12-13 11:12 ` John Garry 2019-12-13 13:18 ` Ming Lei 2019-12-13 15:43 ` John Garry 2019-12-13 17:12 ` Ming Lei 2019-12-13 17:50 ` John Garry 2019-12-14 13:56 ` Marc Zyngier 2019-12-16 10:47 ` John Garry 2019-12-16 11:40 ` Marc Zyngier 2019-12-16 14:17 ` John Garry 2019-12-16 18:00 ` Marc Zyngier [this message] 2019-12-16 18:50 ` John Garry 2019-12-20 11:30 ` John Garry 2019-12-20 14:43 ` Marc Zyngier 2019-12-20 15:38 ` John Garry 2019-12-20 16:16 ` Marc Zyngier 2019-12-20 23:31 ` Ming Lei 2019-12-23 9:07 ` Marc Zyngier 2019-12-23 10:26 ` John Garry 2019-12-23 10:47 ` Marc Zyngier 2019-12-23 11:35 ` John Garry 2019-12-24 1:59 ` Ming Lei 2019-12-24 11:20 ` Marc Zyngier 2019-12-25 0:48 ` Ming Lei 2020-01-02 10:35 ` John Garry 2020-01-03 0:46 ` Ming Lei 2020-01-03 10:41 ` John Garry 2020-01-03 11:29 ` Ming Lei 2020-01-03 11:50 ` John Garry 2020-01-04 12:03 ` Ming Lei 2020-05-30 7:46 ` [tip: irq/core] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs tip-bot2 for Marc Zyngier
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