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From: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
To: "Z.q. Hou" <zhiqiang.hou@nxp.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
	"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>
Cc: Roy Zang <roy.zang@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com>,
	"M.h. Lian" <minghuan.lian@nxp.com>
Subject: Re: [PATCH 2/4] PCI/dwc: Fix the 4GiB outbound window size truncated to zero issue
Date: Mon, 5 Nov 2018 12:25:30 +0000	[thread overview]
Message-ID: <681034bb-f73b-1793-ed48-ff49e8b58cf5@synopsys.com> (raw)
In-Reply-To: <20181025092229.28413-3-Zhiqiang.Hou@nxp.com>

On 25/10/2018 10:22, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> The current type of mem_size is 'u32', so when resource_size()
> return 4G it will be truncated to zero. This patch fix it by
> changing its type to 'u64'.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
>  drivers/pci/controller/dwc/pcie-designware.h | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 2153956a0b20..7ac5989c23ef 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -106,7 +106,7 @@ static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
>  
>  static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
>  					     int type, u64 cpu_addr,
> -					     u64 pci_addr, u32 size)
> +					     u64 pci_addr, u64 size)
>  {
>  	u32 retries, val;
>  
> @@ -141,7 +141,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
>  }
>  
>  void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> -			       u64 cpu_addr, u64 pci_addr, u32 size)
> +			       u64 cpu_addr, u64 pci_addr, u64 size)
>  {
>  	u32 retries, val;
>  
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 9f1a5e399b70..a438c3879aa9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -153,7 +153,7 @@ struct pcie_port {
>  	u32			io_size;
>  	u64			mem_base;
>  	phys_addr_t		mem_bus_addr;
> -	u32			mem_size;
> +	u64			mem_size;
>  	struct resource		*cfg;
>  	struct resource		*io;
>  	struct resource		*mem;
> @@ -238,7 +238,7 @@ int dw_pcie_link_up(struct dw_pcie *pci);
>  int dw_pcie_wait_for_link(struct dw_pcie *pci);
>  void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
>  			       int type, u64 cpu_addr, u64 pci_addr,
> -			       u32 size);
> +			       u64 size);
>  int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
>  			     u64 cpu_addr, enum dw_pcie_as_type as_type);
>  void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
> 

Nice catch! :)

Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>


  reply	other threads:[~2018-11-05 12:29 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-25  9:22 [PATCH 0/4] PCI/dwc: Add more than 4GiB range support Z.q. Hou
2018-10-25  9:22 ` [PATCH 1/4] PCI/dwc: fix potential memory leak Z.q. Hou
2018-11-05 12:18   ` Gustavo Pimentel
2018-10-25  9:22 ` [PATCH 2/4] PCI/dwc: Fix the 4GiB outbound window size truncated to zero issue Z.q. Hou
2018-11-05 12:25   ` Gustavo Pimentel [this message]
2018-10-25  9:22 ` [PATCH 3/4] PCI/layerscape: initialize the number of viewport Z.q. Hou
2018-10-25  9:22 ` [PATCH 4/4] PCI/dwc: Add more than 4GiB range support Z.q. Hou
2018-10-25 11:31   ` kbuild test robot

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