From: Dmitry Osipenko <digetx@gmail.com>
To: Vinod Koul <vkoul@kernel.org>
Cc: Laxman Dewangan <ldewangan@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] dmaengine: tegra: Use relaxed versions of readl/writel
Date: Fri, 26 Apr 2019 15:19:22 +0300 [thread overview]
Message-ID: <68c342e2-5662-5632-82aa-659da0381f54@gmail.com> (raw)
In-Reply-To: <20190426120148.GB28103@vkoul-mobl>
26.04.2019 15:01, Vinod Koul пишет:
> On 25-04-19, 02:17, Dmitry Osipenko wrote:
>> The readl/writel functions are inserting memory barrier in order to
>> ensure that memory stores are completed. On Tegra20 and Tegra30 this
>> results in L2 cache syncing which isn't a cheapest operation. The
>> tegra20-apb-dma driver doesn't need to synchronize generic memory
>> accesses, hence use the relaxed versions of the functions.
>
> Subsystem name is **dmaengine** not dma! Please fix that
>
Looks like you answered to a wrong email.
next prev parent reply other threads:[~2019-04-26 12:19 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-24 23:17 [PATCH v1] dmaengine: tegra: Use relaxed versions of readl/writel Dmitry Osipenko
2019-04-26 9:52 ` Jon Hunter
2019-04-26 10:45 ` Dmitry Osipenko
2019-04-26 11:13 ` Jon Hunter
2019-04-26 12:18 ` Dmitry Osipenko
2019-04-26 12:42 ` Dmitry Osipenko
2019-04-26 13:03 ` Dmitry Osipenko
2019-04-26 15:11 ` Thierry Reding
2019-04-30 12:25 ` Dmitry Osipenko
2019-04-26 12:01 ` Vinod Koul
2019-04-26 12:19 ` Dmitry Osipenko [this message]
2019-04-26 12:47 ` Vinod Koul
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