[PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[John Garry]

This patchset adds some missing uncore PMU events for the hip08 arm64
platform.

The missing events were originally mentioned in
https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.

It also includes a fix for a DDRC eventname.

John Garry (4):
  perf jevents: Fix Hisi hip08 DDRC PMU eventname
  perf jevents: Add some missing events for Hisi hip08 DDRC PMU
  perf jevents: Add some missing events for Hisi hip08 L3C PMU
  perf jevents: Add some missing events for Hisi hip08 HHA PMU

 .../arm64/hisilicon/hip08/uncore-ddrc.json    | 16 +++++-
 .../arm64/hisilicon/hip08/uncore-hha.json     | 23 +++++++-
 .../arm64/hisilicon/hip08/uncore-l3c.json     | 56 +++++++++++++++++++
 3 files changed, 93 insertions(+), 2 deletions(-)

-- 
2.17.1

[PATCH 1/4] perf jevents: Fix Hisi hip08 DDRC PMU eventname

[John Garry]

The "EventName" for the DDRC precharge command event is incorrect, so fix
it.

Fixes: 57cc732479ba ("perf jevents: Add support for Hisi hip08 DDRC PMU aliasing")
Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
index 0d1556fcdffe..99f4fc425564 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
@@ -15,7 +15,7 @@
    },
    {
 	    "EventCode": "0x04",
-	    "EventName": "uncore_hisi_ddrc.flux_wr",
+	    "EventName": "uncore_hisi_ddrc.pre_cmd",
 	    "BriefDescription": "DDRC precharge commands",
 	    "PublicDescription": "DDRC precharge commands",
 	    "Unit": "hisi_sccl,ddrc",
-- 
2.17.1

[PATCH 2/4] perf jevents: Add some missing events for Hisi hip08 DDRC PMU

[John Garry]

Add some more missing events.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../arch/arm64/hisilicon/hip08/uncore-ddrc.json    | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
index 99f4fc425564..7da86942dae2 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
@@ -1,4 +1,18 @@
 [
+   {
+	    "EventCode": "0x00",
+	    "EventName": "uncore_hisi_ddrc.flux_wr",
+	    "BriefDescription": "DDRC total write operations",
+	    "PublicDescription": "DDRC total write operations",
+	    "Unit": "hisi_sccl,ddrc",
+   },
+   {
+	    "EventCode": "0x01",
+	    "EventName": "uncore_hisi_ddrc.flux_rd",
+	    "BriefDescription": "DDRC total read operations",
+	    "PublicDescription": "DDRC total read operations",
+	    "Unit": "hisi_sccl,ddrc",
+   },
    {
 	    "EventCode": "0x02",
 	    "EventName": "uncore_hisi_ddrc.flux_wcmd",
-- 
2.17.1

[PATCH 3/4] perf jevents: Add some missing events for Hisi hip08 L3C PMU

[John Garry]

Add some more missing events.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../arm64/hisilicon/hip08/uncore-l3c.json     | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
index ca48747642e1..f463d0acfaef 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
@@ -34,4 +34,60 @@
 	    "PublicDescription": "l3c precharge commands",
 	    "Unit": "hisi_sccl,l3c",
    },
+   {
+	    "EventCode": "0x20",
+	    "EventName": "uncore_hisi_l3c.rd_spipe",
+	    "BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
+	    "PublicDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x21",
+	    "EventName": "uncore_hisi_l3c.wr_spipe",
+	    "BriefDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
+	    "PublicDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x22",
+	    "EventName": "uncore_hisi_l3c.rd_hit_spipe",
+	    "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C",
+	    "PublicDescription": "Count of the number of read lines that hits in spipe of this L3C",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x23",
+	    "EventName": "uncore_hisi_l3c.wr_hit_spipe",
+	    "BriefDescription": "Count of the number of write lines that hits in spipe of this L3C",
+	    "PublicDescription": "Count of the number of write lines that hits in spipe of this L3C",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x29",
+	    "EventName": "uncore_hisi_l3c.back_invalid",
+	    "BriefDescription": "Count of the number of L3C back invalid operations",
+	    "PublicDescription": "Count of the number of L3C back invalid operations",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x40",
+	    "EventName": "uncore_hisi_l3c.retry_cpu",
+	    "BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations",
+	    "PublicDescription": "Count of the number of retry that L3C suppresses the CPU operations",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x41",
+	    "EventName": "uncore_hisi_l3c.retry_ring",
+	    "BriefDescription": "Count of the number of retry that L3C suppresses the ring operations",
+	    "PublicDescription": "Count of the number of retry that L3C suppresses the ring operations",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x42",
+	    "EventName": "uncore_hisi_l3c.prefetch_drop",
+	    "BriefDescription": "Count of the number of prefetch drops from this L3C",
+	    "PublicDescription": "Count of the number of prefetch drops from this L3C",
+	    "Unit": "hisi_sccl,l3c",
+   },
 ]
-- 
2.17.1

[PATCH 4/4] perf jevents: Add some missing events for Hisi hip08 HHA PMU

[John Garry]

Add some more missing events.

A trivial typo is also fixed.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../arm64/hisilicon/hip08/uncore-hha.json     | 23 ++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json
index 447d3064de90..3be418a248ea 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json
@@ -20,6 +20,13 @@
 	    "PublicDescription": "The number of all operations received by the HHA from another SCCL in this socket",
 	    "Unit": "hisi_sccl,hha",
    },
+   {
+	    "EventCode": "0x03",
+	    "EventName": "uncore_hisi_hha.rx_ccix",
+	    "BriefDescription": "Count of the number of operations that HHA has received from CCIX",
+	    "PublicDescription": "Count of the number of operations that HHA has received from CCIX",
+	    "Unit": "hisi_sccl,hha",
+   },
    {
 	    "EventCode": "0x1c",
 	    "EventName": "uncore_hisi_hha.rd_ddr_64b",
@@ -29,7 +36,7 @@
    },
    {
 	    "EventCode": "0x1d",
-	    "EventName": "uncore_hisi_hha.wr_dr_64b",
+	    "EventName": "uncore_hisi_hha.wr_ddr_64b",
 	    "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
 	    "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
 	    "Unit": "hisi_sccl,hha",
@@ -48,4 +55,18 @@
 	    "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
 	    "Unit": "hisi_sccl,hha",
    },
+   {
+	    "EventCode": "0x20",
+	    "EventName": "uncore_hisi_hha.spill_num",
+	    "BriefDescription": "Count of the number of spill operations that the HHA has sent",
+	    "PublicDescription": "Count of the number of spill operations that the HHA has sent",
+	    "Unit": "hisi_sccl,hha",
+   },
+   {
+	    "EventCode": "0x21",
+	    "EventName": "uncore_hisi_hha.spill_success",
+	    "BriefDescription": "Count of the number of successful spill operations that the HHA has sent",
+	    "PublicDescription": "Count of the number of successful spill operations that the HHA has sent",
+	    "Unit": "hisi_sccl,hha",
+   },
 ]
-- 
2.17.1

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[John Garry]

On 04/09/2019 16:54, John Garry wrote:
> This patchset adds some missing uncore PMU events for the hip08 arm64
> platform.
>
> The missing events were originally mentioned in
> https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.
>
> It also includes a fix for a DDRC eventname.

Hi guys,

Could I get these JSON updates picked up please? Maybe they were missed 
earlier. Let me know if I should re-post.

Thanks in advance,
John

>
> John Garry (4):
>   perf jevents: Fix Hisi hip08 DDRC PMU eventname
>   perf jevents: Add some missing events for Hisi hip08 DDRC PMU
>   perf jevents: Add some missing events for Hisi hip08 L3C PMU
>   perf jevents: Add some missing events for Hisi hip08 HHA PMU
>
>  .../arm64/hisilicon/hip08/uncore-ddrc.json    | 16 +++++-
>  .../arm64/hisilicon/hip08/uncore-hha.json     | 23 +++++++-
>  .../arm64/hisilicon/hip08/uncore-l3c.json     | 56 +++++++++++++++++++
>  3 files changed, 93 insertions(+), 2 deletions(-)
>

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[Arnaldo Carvalho de Melo]

Em Fri, Oct 04, 2019 at 03:30:07PM +0100, John Garry escreveu:
> On 04/09/2019 16:54, John Garry wrote:
> > This patchset adds some missing uncore PMU events for the hip08 arm64
> > platform.
> > 
> > The missing events were originally mentioned in
> > https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.
> > 
> > It also includes a fix for a DDRC eventname.
> 
> Hi guys,
> 
> Could I get these JSON updates picked up please? Maybe they were missed
> earlier. Let me know if I should re-post.

Looking at them now.

- Arnaldo
 
> Thanks in advance,
> John
> 
> > 
> > John Garry (4):
> >   perf jevents: Fix Hisi hip08 DDRC PMU eventname
> >   perf jevents: Add some missing events for Hisi hip08 DDRC PMU
> >   perf jevents: Add some missing events for Hisi hip08 L3C PMU
> >   perf jevents: Add some missing events for Hisi hip08 HHA PMU
> > 
> >  .../arm64/hisilicon/hip08/uncore-ddrc.json    | 16 +++++-
> >  .../arm64/hisilicon/hip08/uncore-hha.json     | 23 +++++++-
> >  .../arm64/hisilicon/hip08/uncore-l3c.json     | 56 +++++++++++++++++++
> >  3 files changed, 93 insertions(+), 2 deletions(-)
> > 
> 

-- 

- Arnaldo

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[Arnaldo Carvalho de Melo]

Em Fri, Oct 04, 2019 at 11:36:58AM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Fri, Oct 04, 2019 at 03:30:07PM +0100, John Garry escreveu:
> > On 04/09/2019 16:54, John Garry wrote:
> > > This patchset adds some missing uncore PMU events for the hip08 arm64
> > > platform.
> > > 
> > > The missing events were originally mentioned in
> > > https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.
> > > 
> > > It also includes a fix for a DDRC eventname.
> > 
> > Hi guys,
> > 
> > Could I get these JSON updates picked up please? Maybe they were missed
> > earlier. Let me know if I should re-post.
> 
> Looking at them now.

It would be really good if somehow we managed to have someone from the
ARM community to check and provide a Reviewed-by for those, i.e. someone
else than the poster to look at it and check that its ok, would that be
possible?

- Arnaldo
 
> - Arnaldo
>  
> > Thanks in advance,
> > John
> > 
> > > 
> > > John Garry (4):
> > >   perf jevents: Fix Hisi hip08 DDRC PMU eventname
> > >   perf jevents: Add some missing events for Hisi hip08 DDRC PMU
> > >   perf jevents: Add some missing events for Hisi hip08 L3C PMU
> > >   perf jevents: Add some missing events for Hisi hip08 HHA PMU
> > > 
> > >  .../arm64/hisilicon/hip08/uncore-ddrc.json    | 16 +++++-
> > >  .../arm64/hisilicon/hip08/uncore-hha.json     | 23 +++++++-
> > >  .../arm64/hisilicon/hip08/uncore-l3c.json     | 56 +++++++++++++++++++
> > >  3 files changed, 93 insertions(+), 2 deletions(-)
> > > 
> > 
> 
> -- 
> 
> - Arnaldo

-- 

- Arnaldo

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[Will Deacon]

On Fri, Oct 04, 2019 at 11:38:35AM -0300, Arnaldo Carvalho de Melo wrote:
> Em Fri, Oct 04, 2019 at 11:36:58AM -0300, Arnaldo Carvalho de Melo escreveu:
> > Em Fri, Oct 04, 2019 at 03:30:07PM +0100, John Garry escreveu:
> > > On 04/09/2019 16:54, John Garry wrote:
> > > > This patchset adds some missing uncore PMU events for the hip08 arm64
> > > > platform.
> > > > 
> > > > The missing events were originally mentioned in
> > > > https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.
> > > > 
> > > > It also includes a fix for a DDRC eventname.
> > > 
> > > Hi guys,
> > > 
> > > Could I get these JSON updates picked up please? Maybe they were missed
> > > earlier. Let me know if I should re-post.
> > 
> > Looking at them now.
> 
> It would be really good if somehow we managed to have someone from the
> ARM community to check and provide a Reviewed-by for those, i.e. someone
> else than the poster to look at it and check that its ok, would that be
> possible?

The patches look fine to me, but the IP being supported here is designed
by Hisilicon so my Arm knowledge isn't very helpful as it's outside the
scope of the architecture.

Will

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[John Garry]

On 04/10/2019 15:38, Arnaldo Carvalho de Melo wrote:
> Em Fri, Oct 04, 2019 at 11:36:58AM -0300, Arnaldo Carvalho de Melo escreveu:
>> Em Fri, Oct 04, 2019 at 03:30:07PM +0100, John Garry escreveu:
>>> On 04/09/2019 16:54, John Garry wrote:
>>>> This patchset adds some missing uncore PMU events for the hip08 arm64
>>>> platform.
>>>>
>>>> The missing events were originally mentioned in
>>>> https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.
>>>>
>>>> It also includes a fix for a DDRC eventname.
>>>
>>> Hi guys,
>>>
>>> Could I get these JSON updates picked up please? Maybe they were missed
>>> earlier. Let me know if I should re-post.
>>
>> Looking at them now.
>
> It would be really good if somehow we managed to have someone from the
> ARM community to check and provide a Reviewed-by for those, i.e. someone
> else than the poster to look at it and check that its ok, would that be
> possible?

Hi Arnaldo,

For this specific case, I'm not sure how much traction or value there 
would be since we're just adding some missing events for custom IP.

But I do agree that more review of JSONs from the community is required 
- as I brought up here regarding a recent addition: 
https://lore.kernel.org/lkml/749a0b8e-2bfd-28f6-b34d-dc72ef3d3a74@huawei.com/

Can we enforce that at least linux-arm-kernel@lists.infradead.org and/or 
get_maintainer.pl results is cc'ed on anything ARM specific as a start?

Cheers,
John

>
> - Arnaldo
>
>> - Arnaldo
>>
>>> Thanks in advance,
>>> John
>>>
>>>>
>>>> John Garry (4):
>>>>   perf jevents: Fix Hisi hip08 DDRC PMU eventname
>>>>   perf jevents: Add some missing events for Hisi hip08 DDRC PMU
>>>>   perf jevents: Add some missing events for Hisi hip08 L3C PMU
>>>>   perf jevents: Add some missing events for Hisi hip08 HHA PMU
>>>>
>>>>  .../arm64/hisilicon/hip08/uncore-ddrc.json    | 16 +++++-
>>>>  .../arm64/hisilicon/hip08/uncore-hha.json     | 23 +++++++-
>>>>  .../arm64/hisilicon/hip08/uncore-l3c.json     | 56 +++++++++++++++++++
>>>>  3 files changed, 93 insertions(+), 2 deletions(-)
>>>>
>>>
>>
>> --
>>
>> - Arnaldo
>

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[Arnaldo Carvalho de Melo]

Em Fri, Oct 04, 2019 at 03:59:44PM +0100, John Garry escreveu:
> On 04/10/2019 15:38, Arnaldo Carvalho de Melo wrote:
> > Em Fri, Oct 04, 2019 at 11:36:58AM -0300, Arnaldo Carvalho de Melo escreveu:
> > > Em Fri, Oct 04, 2019 at 03:30:07PM +0100, John Garry escreveu:
> > > > On 04/09/2019 16:54, John Garry wrote:
> > > > > This patchset adds some missing uncore PMU events for the hip08 arm64
> > > > > platform.

> > > > > The missing events were originally mentioned in
> > > > > https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.

> > > > > It also includes a fix for a DDRC eventname.

> > > > Could I get these JSON updates picked up please? Maybe they were missed
> > > > earlier. Let me know if I should re-post.

> > > Looking at them now.

> > It would be really good if somehow we managed to have someone from the
> > ARM community to check and provide a Reviewed-by for those, i.e. someone
> > else than the poster to look at it and check that its ok, would that be
> > possible?
 
> For this specific case, I'm not sure how much traction or value there would
> be since we're just adding some missing events for custom IP.

Someone else inside your organization? If nobody is available, then so
be it, let that be clear in the JSON file (see below) and then I
wouldn't be waiting for acks/reviewed-by messages for such cases.
 
> But I do agree that more review of JSONs from the community is required - as
> I brought up here regarding a recent addition:
> https://lore.kernel.org/lkml/749a0b8e-2bfd-28f6-b34d-dc72ef3d3a74@huawei.com/
> 
> Can we enforce that at least linux-arm-kernel@lists.infradead.org and/or
> get_maintainer.pl results is cc'ed on anything ARM specific as a start?

I think this should be the case, would you be willing to add a note to
that effect at the top of the JSON files?

And an extra note at tools/perf/pmu-events/README telling users to look
at the json files to figure out what Reviewed-by tags are required for
something to get merged? One extra Reviewed-by would be ok? Who would be
the reviewers for each arch? Would that be at the top of the JSON file?

- Arnaldo

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[John Garry]

>
>>>>>> The missing events were originally mentioned in
>>>>>> https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.
>
>>>>>> It also includes a fix for a DDRC eventname.
>
>>>>> Could I get these JSON updates picked up please? Maybe they were missed
>>>>> earlier. Let me know if I should re-post.
>
>>>> Looking at them now.
>
>>> It would be really good if somehow we managed to have someone from the
>>> ARM community to check and provide a Reviewed-by for those, i.e. someone
>>> else than the poster to look at it and check that its ok, would that be
>>> possible?
>
>> For this specific case, I'm not sure how much traction or value there would
>> be since we're just adding some missing events for custom IP.
>
> Someone else inside your organization?

For this, sure. Colleague Shaokun (cc'ed) provided me the metadata for 
these JSON additions, so when he returns from national vacation I can 
ask him to provide necessary tags.

  If nobody is available, then so
> be it, let that be clear in the JSON file (see below) and then I
> wouldn't be waiting for acks/reviewed-by messages for such cases.
>
>> But I do agree that more review of JSONs from the community is required - as
>> I brought up here regarding a recent addition:
>> https://lore.kernel.org/lkml/749a0b8e-2bfd-28f6-b34d-dc72ef3d3a74@huawei.com/
>>
>> Can we enforce that at least linux-arm-kernel@lists.infradead.org and/or
>> get_maintainer.pl results is cc'ed on anything ARM specific as a start?
>
> I think this should be the case, would you be willing to add a note to
> that effect at the top of the JSON files?

Adding notes to JSONs would be painful unless the parser is updated to 
to filter them out. And, as I understand, the x86 JSONs are 
autogenerated, so that tooling would need to handle this also.

>
> And an extra note at tools/perf/pmu-events/README telling users to look
> at the json files to figure out what Reviewed-by tags are required for
> something to get merged? One extra Reviewed-by would be ok?Who would be
> the reviewers for each arch? Would that be at the top of the JSON file?

There is no per-arch JSON, and, in addition, I think that would be hard 
to formulate such formal rules.

As an alternative, how about just add a maintainers entry for reviewers 
per arch? As a start, I don't mind being added there for arm64:

--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12767,6 +12767,10 @@ F:     arch/*/events/*
  F:     arch/*/events/*/*
  F:     tools/perf/

+PERFORMANCE EVENTS SUBSYSTEM ARM64 PMU EVENTS
+R:     John Garry <john.garry@huawei.com>
+F:     tools/perf/pmu-events/arch/arm64
+

Patches per-arch should have some nod/tag from a member of the 
respective list. Or at very least be cc'ed :)

Thanks,
John

>
> - Arnaldo
>
> .
>

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[Arnaldo Carvalho de Melo]

Em Fri, Oct 04, 2019 at 05:30:46PM +0100, John Garry escreveu:
> > 
> > > > > > > The missing events were originally mentioned in
> > > > > > > https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.
> > 
> > > > > > > It also includes a fix for a DDRC eventname.
> > 
> > > > > > Could I get these JSON updates picked up please? Maybe they were missed
> > > > > > earlier. Let me know if I should re-post.
> > 
> > > > > Looking at them now.
> > 
> > > > It would be really good if somehow we managed to have someone from the
> > > > ARM community to check and provide a Reviewed-by for those, i.e. someone
> > > > else than the poster to look at it and check that its ok, would that be
> > > > possible?
> > 
> > > For this specific case, I'm not sure how much traction or value there would
> > > be since we're just adding some missing events for custom IP.
> > 
> > Someone else inside your organization?
> 
> For this, sure. Colleague Shaokun (cc'ed) provided me the metadata for these
> JSON additions, so when he returns from national vacation I can ask him to
> provide necessary tags.

Ok
 
>  If nobody is available, then so
> > be it, let that be clear in the JSON file (see below) and then I
> > wouldn't be waiting for acks/reviewed-by messages for such cases.
> > 
> > > But I do agree that more review of JSONs from the community is required - as
> > > I brought up here regarding a recent addition:
> > > https://lore.kernel.org/lkml/749a0b8e-2bfd-28f6-b34d-dc72ef3d3a74@huawei.com/
> > > 
> > > Can we enforce that at least linux-arm-kernel@lists.infradead.org and/or
> > > get_maintainer.pl results is cc'ed on anything ARM specific as a start?
> > 
> > I think this should be the case, would you be willing to add a note to
> > that effect at the top of the JSON files?
> 
> Adding notes to JSONs would be painful unless the parser is updated to to
> filter them out. And, as I understand, the x86 JSONs are autogenerated, so
> that tooling would need to handle this also.

Ok
 
> > 
> > And an extra note at tools/perf/pmu-events/README telling users to look
> > at the json files to figure out what Reviewed-by tags are required for
> > something to get merged? One extra Reviewed-by would be ok?Who would be
> > the reviewers for each arch? Would that be at the top of the JSON file?
> 
> There is no per-arch JSON, and, in addition, I think that would be hard to
> formulate such formal rules.

Ok
 
> As an alternative, how about just add a maintainers entry for reviewers per
> arch? As a start, I don't mind being added there for arm64:
> 
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -12767,6 +12767,10 @@ F:     arch/*/events/*
>  F:     arch/*/events/*/*
>  F:     tools/perf/
> 
> +PERFORMANCE EVENTS SUBSYSTEM ARM64 PMU EVENTS
> +R:     John Garry <john.garry@huawei.com>
> +F:     tools/perf/pmu-events/arch/arm64
> +
> 
> Patches per-arch should have some nod/tag from a member of the respective
> list. Or at very least be cc'ed :)

Another Ok, please send a formal patch, and it would be really nice if
the other ARM folks would... Ack that ;-) :-) And provide extra entries
for the other pmu-events directories or even for specific files, which
is a possibility, right?

On my side I'll script a bit more and make sure that a post commit hook
warns me if the right tag is not present.

- Arnaldo

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[John Garry]

>
>> As an alternative, how about just add a maintainers entry for reviewers per
>> arch? As a start, I don't mind being added there for arm64:
>>
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -12767,6 +12767,10 @@ F:     arch/*/events/*
>>  F:     arch/*/events/*/*
>>  F:     tools/perf/
>>
>> +PERFORMANCE EVENTS SUBSYSTEM ARM64 PMU EVENTS
>> +R:     John Garry <john.garry@huawei.com>
>> +F:     tools/perf/pmu-events/arch/arm64
>> +
>>
>> Patches per-arch should have some nod/tag from a member of the respective
>> list. Or at very least be cc'ed :)
>
> Another Ok, please send a formal patch, and it would be really nice if
> the other ARM folks would... Ack that ;-) :-) And provide extra entries
> for the other pmu-events directories or even for specific files, which
> is a possibility, right?

ok, can do. Will has kindly agreed to have his name added to the 
MAINTAINERS entry (thanks). Other Cc's from ARM community may also be 
interested to be included - shout if so.

So I'll just include tools/perf/pmu-events/arch/arm64 for now.

The code in tools/perf/pmu-events/. should be generic for all 
architectures, while I'd say tools/perf/arch/arm64 is not strictly related.

Thanks,
John

>
> On my side I'll script a bit more and make sure that a post commit hook
> warns me if the right tag is not present.
>
> - Arnaldo
>
> .
>

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[Shaokun Zhang]

Hi John,

Thanks for your nice work, these are useful for performance profiling
if anyone is unfamiliar with the uncore PMU events on hip08.
For this patchset, please feel free to add
Reviewed-by: Shaokun Zhang <zhangshaokun@hisilicon.com>

Thanks,
Shaokun

On 2019/9/4 23:54, John Garry wrote:
> This patchset adds some missing uncore PMU events for the hip08 arm64
> platform.
> 
> The missing events were originally mentioned in
> https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.
> 
> It also includes a fix for a DDRC eventname.
> 
> John Garry (4):
>   perf jevents: Fix Hisi hip08 DDRC PMU eventname
>   perf jevents: Add some missing events for Hisi hip08 DDRC PMU
>   perf jevents: Add some missing events for Hisi hip08 L3C PMU
>   perf jevents: Add some missing events for Hisi hip08 HHA PMU
> 
>  .../arm64/hisilicon/hip08/uncore-ddrc.json    | 16 +++++-
>  .../arm64/hisilicon/hip08/uncore-hha.json     | 23 +++++++-
>  .../arm64/hisilicon/hip08/uncore-l3c.json     | 56 +++++++++++++++++++
>  3 files changed, 93 insertions(+), 2 deletions(-)
> 

Re: [PATCH 0/4] HiSilicon hip08 uncore PMU events additions

[Arnaldo Carvalho de Melo]

Em Wed, Oct 09, 2019 at 09:14:45AM +0800, Shaokun Zhang escreveu:
> Hi John,
> 
> Thanks for your nice work, these are useful for performance profiling
> if anyone is unfamiliar with the uncore PMU events on hip08.

> For this patchset, please feel free to add
> Reviewed-by: Shaokun Zhang <zhangshaokun@hisilicon.com>

Thanks, added and applied,

- Arnaldo
 
> Thanks,
> Shaokun
> 
> On 2019/9/4 23:54, John Garry wrote:
> > This patchset adds some missing uncore PMU events for the hip08 arm64
> > platform.
> > 
> > The missing events were originally mentioned in
> > https://lkml.org/lkml/2019/6/14/645, when upstreaming the JSONs initially.
> > 
> > It also includes a fix for a DDRC eventname.
> > 
> > John Garry (4):
> >   perf jevents: Fix Hisi hip08 DDRC PMU eventname
> >   perf jevents: Add some missing events for Hisi hip08 DDRC PMU
> >   perf jevents: Add some missing events for Hisi hip08 L3C PMU
> >   perf jevents: Add some missing events for Hisi hip08 HHA PMU
> > 
> >  .../arm64/hisilicon/hip08/uncore-ddrc.json    | 16 +++++-
> >  .../arm64/hisilicon/hip08/uncore-hha.json     | 23 +++++++-
> >  .../arm64/hisilicon/hip08/uncore-l3c.json     | 56 +++++++++++++++++++
> >  3 files changed, 93 insertions(+), 2 deletions(-)
> > 

-- 

- Arnaldo

[tip: perf/core] perf vendor events arm64: Add some missing events for Hisi hip08 HHA PMU

[tip-bot2 for John Garry]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     2b7847158120136c4b23684c768a82d571ee59bf
Gitweb:        https://git.kernel.org/tip/2b7847158120136c4b23684c768a82d571ee59bf
Author:        John Garry <john.garry@huawei.com>
AuthorDate:    Wed, 04 Sep 2019 23:54:44 +08:00
Committer:     Arnaldo Carvalho de Melo <acme@redhat.com>
CommitterDate: Tue, 15 Oct 2019 13:03:58 -03:00

perf vendor events arm64: Add some missing events for Hisi hip08 HHA PMU

Add some more missing events.

A trivial typo is also fixed.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linuxarm@huawei.com
Link: http://lore.kernel.org/lkml/1567612484-195727-5-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json
index 447d306..3be418a 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json
@@ -21,6 +21,13 @@
 	    "Unit": "hisi_sccl,hha",
    },
    {
+	    "EventCode": "0x03",
+	    "EventName": "uncore_hisi_hha.rx_ccix",
+	    "BriefDescription": "Count of the number of operations that HHA has received from CCIX",
+	    "PublicDescription": "Count of the number of operations that HHA has received from CCIX",
+	    "Unit": "hisi_sccl,hha",
+   },
+   {
 	    "EventCode": "0x1c",
 	    "EventName": "uncore_hisi_hha.rd_ddr_64b",
 	    "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
@@ -29,7 +36,7 @@
    },
    {
 	    "EventCode": "0x1d",
-	    "EventName": "uncore_hisi_hha.wr_dr_64b",
+	    "EventName": "uncore_hisi_hha.wr_ddr_64b",
 	    "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
 	    "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
 	    "Unit": "hisi_sccl,hha",
@@ -48,4 +55,18 @@
 	    "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
 	    "Unit": "hisi_sccl,hha",
    },
+   {
+	    "EventCode": "0x20",
+	    "EventName": "uncore_hisi_hha.spill_num",
+	    "BriefDescription": "Count of the number of spill operations that the HHA has sent",
+	    "PublicDescription": "Count of the number of spill operations that the HHA has sent",
+	    "Unit": "hisi_sccl,hha",
+   },
+   {
+	    "EventCode": "0x21",
+	    "EventName": "uncore_hisi_hha.spill_success",
+	    "BriefDescription": "Count of the number of successful spill operations that the HHA has sent",
+	    "PublicDescription": "Count of the number of successful spill operations that the HHA has sent",
+	    "Unit": "hisi_sccl,hha",
+   },
 ]

[tip: perf/core] perf vendor events arm64: Add some missing events for Hisi hip08 L3C PMU

[tip-bot2 for John Garry]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     e3ae569541802a6c9e89ab1f0f3ff613a5a1237b
Gitweb:        https://git.kernel.org/tip/e3ae569541802a6c9e89ab1f0f3ff613a5a1237b
Author:        John Garry <john.garry@huawei.com>
AuthorDate:    Wed, 04 Sep 2019 23:54:43 +08:00
Committer:     Arnaldo Carvalho de Melo <acme@redhat.com>
CommitterDate: Tue, 15 Oct 2019 13:03:58 -03:00

perf vendor events arm64: Add some missing events for Hisi hip08 L3C PMU

Add some more missing events.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linuxarm@huawei.com
Link: http://lore.kernel.org/lkml/1567612484-195727-4-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
index ca48747..f463d0a 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
@@ -34,4 +34,60 @@
 	    "PublicDescription": "l3c precharge commands",
 	    "Unit": "hisi_sccl,l3c",
    },
+   {
+	    "EventCode": "0x20",
+	    "EventName": "uncore_hisi_l3c.rd_spipe",
+	    "BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
+	    "PublicDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x21",
+	    "EventName": "uncore_hisi_l3c.wr_spipe",
+	    "BriefDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
+	    "PublicDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x22",
+	    "EventName": "uncore_hisi_l3c.rd_hit_spipe",
+	    "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C",
+	    "PublicDescription": "Count of the number of read lines that hits in spipe of this L3C",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x23",
+	    "EventName": "uncore_hisi_l3c.wr_hit_spipe",
+	    "BriefDescription": "Count of the number of write lines that hits in spipe of this L3C",
+	    "PublicDescription": "Count of the number of write lines that hits in spipe of this L3C",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x29",
+	    "EventName": "uncore_hisi_l3c.back_invalid",
+	    "BriefDescription": "Count of the number of L3C back invalid operations",
+	    "PublicDescription": "Count of the number of L3C back invalid operations",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x40",
+	    "EventName": "uncore_hisi_l3c.retry_cpu",
+	    "BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations",
+	    "PublicDescription": "Count of the number of retry that L3C suppresses the CPU operations",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x41",
+	    "EventName": "uncore_hisi_l3c.retry_ring",
+	    "BriefDescription": "Count of the number of retry that L3C suppresses the ring operations",
+	    "PublicDescription": "Count of the number of retry that L3C suppresses the ring operations",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x42",
+	    "EventName": "uncore_hisi_l3c.prefetch_drop",
+	    "BriefDescription": "Count of the number of prefetch drops from this L3C",
+	    "PublicDescription": "Count of the number of prefetch drops from this L3C",
+	    "Unit": "hisi_sccl,l3c",
+   },
 ]

[tip: perf/core] perf vendor events arm64: Fix Hisi hip08 DDRC PMU eventname

[tip-bot2 for John Garry]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     84b0975f4853ba32d2d9b3c19ffa2b947f023fb3
Gitweb:        https://git.kernel.org/tip/84b0975f4853ba32d2d9b3c19ffa2b947f023fb3
Author:        John Garry <john.garry@huawei.com>
AuthorDate:    Wed, 04 Sep 2019 23:54:41 +08:00
Committer:     Arnaldo Carvalho de Melo <acme@redhat.com>
CommitterDate: Tue, 15 Oct 2019 13:03:58 -03:00

perf vendor events arm64: Fix Hisi hip08 DDRC PMU eventname

The "EventName" for the DDRC precharge command event is incorrect, so
fix it.

Fixes: 57cc732479ba ("perf jevents: Add support for Hisi hip08 DDRC PMU aliasing")
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linuxarm@huawei.com
Link: http://lore.kernel.org/lkml/1567612484-195727-2-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
index 0d1556f..99f4fc4 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
@@ -15,7 +15,7 @@
    },
    {
 	    "EventCode": "0x04",
-	    "EventName": "uncore_hisi_ddrc.flux_wr",
+	    "EventName": "uncore_hisi_ddrc.pre_cmd",
 	    "BriefDescription": "DDRC precharge commands",
 	    "PublicDescription": "DDRC precharge commands",
 	    "Unit": "hisi_sccl,ddrc",

[tip: perf/core] perf vendor events arm64: Add some missing events for Hisi hip08 DDRC PMU

[tip-bot2 for John Garry]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     1410732a1b642ba82730a95bdf7f4dafbac1891a
Gitweb:        https://git.kernel.org/tip/1410732a1b642ba82730a95bdf7f4dafbac1891a
Author:        John Garry <john.garry@huawei.com>
AuthorDate:    Wed, 04 Sep 2019 23:54:42 +08:00
Committer:     Arnaldo Carvalho de Melo <acme@redhat.com>
CommitterDate: Tue, 15 Oct 2019 13:03:58 -03:00

perf vendor events arm64: Add some missing events for Hisi hip08 DDRC PMU

Add some more missing events.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linuxarm@huawei.com
Link: http://lore.kernel.org/lkml/1567612484-195727-3-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
index 99f4fc4..7da8694 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json
@@ -1,5 +1,19 @@
 [
    {
+	    "EventCode": "0x00",
+	    "EventName": "uncore_hisi_ddrc.flux_wr",
+	    "BriefDescription": "DDRC total write operations",
+	    "PublicDescription": "DDRC total write operations",
+	    "Unit": "hisi_sccl,ddrc",
+   },
+   {
+	    "EventCode": "0x01",
+	    "EventName": "uncore_hisi_ddrc.flux_rd",
+	    "BriefDescription": "DDRC total read operations",
+	    "PublicDescription": "DDRC total read operations",
+	    "Unit": "hisi_sccl,ddrc",
+   },
+   {
 	    "EventCode": "0x02",
 	    "EventName": "uncore_hisi_ddrc.flux_wcmd",
 	    "BriefDescription": "DDRC write commands",