From: Sinan Kaya <okaya@kernel.org>
To: Christoph Hellwig <hch@lst.de>, okaya@codeaurora.org
Cc: Tony Luck <tony.luck@intel.com>,
Fenghua Yu <fenghua.yu@intel.com>, Arnd Bergmann <arnd@arndb.de>,
linux-ia64@vger.kernel.org, linux-arch@vger.kernel.org,
linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org
Subject: Re: [PATCH] ia64: fix barrier placement for write* / dma mapping
Date: Wed, 1 Aug 2018 01:00:32 -0700 [thread overview]
Message-ID: <6ac80566-be1b-3dfc-e6b7-3c38131673ef@kernel.org> (raw)
In-Reply-To: <20180801072947.GD20224@lst.de>
On 8/1/2018 12:29 AM, Christoph Hellwig wrote:
>> I asked this question to Tony Luck before. If I remember right,
>> his answer was:
>>
>> CPU guarantees outstanding writes to be flushed when a register write
>> instruction is executed and an additional barrier instruction is not
>> needed.
> That would be great. It still doesn't explain the barriers in the
> dma sync routines. Those have been there since the following commit
> in the history tree:
Yeah, I'll let Tony confirm my understanding.
prev parent reply other threads:[~2018-08-01 8:00 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-31 17:20 barriers vs I/O and DMA for ia64 Christoph Hellwig
2018-07-31 17:20 ` [PATCH] ia64: fix barrier placement for write* / dma mapping Christoph Hellwig
2018-08-01 6:41 ` okaya
2018-08-01 7:29 ` Christoph Hellwig
2018-08-01 8:00 ` Sinan Kaya [this message]
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