From: Ben Dooks <ben.dooks@sifive.com>
To: Conor.Dooley@microchip.com, palmer@dabbelt.com,
paul.walmsley@sifive.com, aou@eecs.berkeley.edu,
greentime.hu@sifive.com, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org
Subject: Re: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache
Date: Tue, 30 Aug 2022 13:58:12 +0100 [thread overview]
Message-ID: <6b6837c1-5a2c-567b-ba64-72a1dca38807@sifive.com> (raw)
In-Reply-To: <b810d354-18f3-9ae0-6310-57d9e36f4f9b@microchip.com>
On 30/08/2022 13:56, Conor.Dooley@microchip.com wrote:
> On 30/08/2022 13:51, Ben Dooks wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> With newer cores such as the p550, the SiFive composable cache can be
>> a level 3 cache. Update the cache level to be one of 2 or 3.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>> ---
>> Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>> index 1a64a5384e36..6190deb65455 100644
>> --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
>> @@ -45,7 +45,7 @@ properties:
>> const: 64
>>
>> cache-level:
>> - const: 2
>> + enum: [2, 3]
>
> Do we want to enforce the cache level like we currently do for
> interrupts and cache-sets?
Not sure on that, for the P550 cores the ccache is going to be level3
and my colleague has said it does confuse some tooling if the level is
not set correctly.
--
Ben
next prev parent reply other threads:[~2022-08-30 12:58 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-29 6:21 [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE Zong Li
2022-08-29 6:22 ` [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache Zong Li
2022-08-29 6:45 ` Conor.Dooley
2022-08-29 7:38 ` Zong Li
2022-08-29 18:42 ` Rob Herring
2022-08-30 2:57 ` Zong Li
2022-10-07 2:58 ` Palmer Dabbelt
2022-10-07 3:51 ` Zong Li
2022-08-29 6:22 ` [PATCH 2/3] soc: sifive: l2 cache: Rename " Zong Li
2022-08-29 7:05 ` Conor.Dooley
2022-08-29 8:40 ` Zong Li
2022-08-30 8:41 ` Conor.Dooley
2022-08-31 5:31 ` Zong Li
2022-08-30 8:18 ` Ben Dooks
2022-08-29 6:22 ` [PATCH 3/3] EDAC/sifive: use sifive_ccache instead of sifive_l2 Zong Li
2022-10-07 2:58 ` Palmer Dabbelt
2022-08-30 7:59 ` [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE Ben Dooks
2022-08-31 8:23 ` Zong Li
2022-08-30 8:26 ` [PATCH] soc: sifive: ccache: reduce printing on init Ben Dooks
2022-08-30 16:30 ` Conor.Dooley
2022-08-30 17:03 ` Ben Dooks
2022-08-31 5:22 ` Zong Li
2022-08-31 15:55 ` Ben Dooks
2022-09-01 8:34 ` Zong Li
2022-08-30 8:36 ` [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache Ben Dooks
2022-08-30 12:47 ` Rob Herring
2022-08-30 12:51 ` [RESEND PATCH] " Ben Dooks
2022-08-30 12:56 ` Conor.Dooley
2022-08-30 12:58 ` Ben Dooks [this message]
2022-08-30 13:49 ` Conor.Dooley
2022-08-30 16:49 ` Ben Dooks
2022-08-30 17:08 ` Conor.Dooley
2022-08-31 5:17 ` Zong Li
2022-08-31 6:25 ` Conor.Dooley
2022-09-02 19:36 ` Rob Herring
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