From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936256AbdAECcB (ORCPT ); Wed, 4 Jan 2017 21:32:01 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:47179 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934316AbdAECb6 (ORCPT ); Wed, 4 Jan 2017 21:31:58 -0500 X-AuditID: b6c32a2d-f79a76d0000074b4-d6-586dadba8f48 Subject: Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework To: Krzysztof Kozlowski Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, kgene@kernel.org, kishon@ti.com, jingoohan1@gmail.com, vivek.gautam@codeaurora.org, pankaj.dubey@samsung.com, alim.akhtar@samsung.com, cpgs@samsung.com From: Jaehoon Chung Message-id: <6cb5851e-d9c9-cdaa-22a0-2f3153b02a99@samsung.com> Date: Thu, 05 Jan 2017 11:21:44 +0900 User-Agent: Mozilla/5.0 (X11; Linux i686; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-version: 1.0 In-reply-to: <20170104175004.bfob5p3esfn2bfai@kozik-lap> Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHJsWRmVeSWpSXmKPExsWy7bCmuu6utbkRBn/mGFs8mLeNzWJJU4bF y0OaFvOPnGO1WPFlJrtF/+PXzBYXnvawWZw/v4Hd4vKuOWwWZ+cdZ7OYcX4fk8XS6xeZLBZt /cJu0br3CLvFiZ87mB34PdbMW8Pocbmvl8lj56y77B4LNpV6bFrVyebRt2UVo8fxG9uZPD5v kgvgiEq1yUhNTEktUkjNS85PycxLt1XyDo53jjc1MzDUNbS0MFdSyEvMTbVVcvEJ0HXLzAE6 XUmhLDGnFCgUkFhcrKRvZ1OUX1qSqpCRX1xiqxRtaGikZ2hgrmdkZKRnYhxrZWQKVJKQmtH0 9RR7wXKdiglLL7I3MJ5X6WLk5JAQMJFYt/U/E4QtJnHh3nq2LkYuDiGBpYwS50+tZIFw2pkk ZjdeZYbpOHR0KiNEYg6jxLQJq6Cce4wSz/qesoNUCQsESXx5CdEhIqApcf3vd1YQm1ngDpPE tuVCIDabgI7E9m/HwXbzCthJbG38xwhiswioSizcNQVsjqhAmMTm+y/ZIWoEJX5MvscCYnMK WEjMu7SbBWKmpsSLL5OgbHmJzWveMoMcJCHwk11i2d1TQAkOIEdWYtMBqA9cJH6cbmGDsIUl Xh3fwg5hS0v8XXqLEaK3m1Hi35eNbBBOD6PEra2roaFkLHH/wT1miG18Er2/nzBBLOCV6GgT gijxkJg8YSfUAkeJrssvoIH6nlHicstXtgmM8rOQPDQLyROzkDyxgJF5FaNYakFxbnpqsWmB kV5xYm5xaV66XnJ+7iZGcNrV0t3B+GWB9yFGAQ5GJR5eS9/cCCHWxLLiytxDjBIczEoivDyr gEK8KYmVValF+fFFpTmpxYcYTYGBPJFZSjQ5H5gT8kriDU3MDE2MLIHQ3NBcSZx3QYV1hJBA emJJanZqakFqEUwfEwenVANj01eDFQsv6UocSTnN/6FvRpXl2dQZtzv2tbf92fBgxnLLp2Wf ZvBPbfX/9uW0SV1t5o5nay36vBP+LHrlxb3U8maBra/oDw37/DKXvErFT5p3OQ9OWam/Os3q uk0256q5+zo4n9xVnPV95cM9D68/ev9k5VLRQPP+r+5J62QCAze+EucOYtX2VmIpzkg01GIu Kk4EANrTOg3RAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrGIsWRmVeSWpSXmKPExsVy+t9jQd2da3MjDM5MU7J4MG8bm8WSpgyL l4c0LeYfOcdqseLLTHaL/sevmS0uPO1hszh/fgO7xeVdc9gszs47zmYx4/w+Joul1y8yWSza +oXdonXvEXaLEz93MDvwe6yZt4bR43JfL5PHzll32T0WbCr12LSqk82jb8sqRo/jN7YzeXze JBfAEeVmk5GamJJapJCal5yfkpmXbqsUGuKma6GkkJeYm2qrFKHrGxKkpFCWmFMK5BkZoAEH 5wD3YCV9uwS3jKavp9gLlutUTFh6kb2B8bxKFyMnh4SAicSho1MZIWwxiQv31rOB2EICsxgl brRA2Q8YJd4eNwWxhQUCJLr6zzGB2CICmhLX/35n7WLkAqp5zyix71EvO4jDLHCHSWJd/2V2 kCo2AR2J7d+Og3XwCthJbG38B7aNRUBVYuGuKUA1HByiAmESzxudIEoEJX5MvscCYnMKWEjM u7SbBaSEWUBdYsqUXJAws4C8xOY1b5knMAIdidAxC6FqFpKqBYzMqxglUguSC4qT0nON8lLL 9YoTc4tL89L1kvNzNzGC4/iZ9A7Gw7vcDzEKcDAq8fB2/M2JEGJNLCuuzD3EKMHBrCTCy7Mq N0KINyWxsiq1KD++qDQntfgQoynQFxOZpUST84EpJq8k3tDE3MTc2MDC3NLSxEhJnLdx9rNw IYH0xJLU7NTUgtQimD4mDk6pBkaLQpeG1U2zV9z4b2P7Zq/8W8G+s7d+yig7SXq48GX8qA1f 2MtSoHBKJHNl0vQn/IqydjWCPBdML3/psjAL/NR1cIKOT+RVY3mpjfIqk81FXf/PW2M0UfHK xCVv6u+s7YxLEJT5bPJd3jf9hERwea2fevzNz0FNZ5f+e3Bx4+xTqanP935sfKHEUpyRaKjF XFScCACWbzL1+QIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170105022145epcas5p3a28575076a7853143b8c271ba0222b21 X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?7KCV7J6s7ZuIG1RpemVuIFBsYXRmb3JtIExhYihTL1fshLw=?= =?UTF-8?B?7YSwKRvsgrzshLHsoITsnpAbUzUo7LGF7J6EKS/ssYXsnoQ=?= X-Global-Sender: =?UTF-8?B?SmFlaG9vbiBDaHVuZxtUaXplbiBQbGF0Zm9ybSBMYWIuG1Nh?= =?UTF-8?B?bXN1bmcgRWxlY3Ryb25pY3MbUzUvU2VuaW9yIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG1NUQUYbQzEwVjgxMTE=?= CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-HopCount: 7 X-CMS-RootMailID: 20170104123436epcas1p1651443c5fe13f67006864aed2f70fa9d X-RootMTR: 20170104123436epcas1p1651443c5fe13f67006864aed2f70fa9d References: <20170104123435.30740-1-jh80.chung@samsung.com> <20170104123435.30740-5-jh80.chung@samsung.com> <20170104175004.bfob5p3esfn2bfai@kozik-lap> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/05/2017 02:50 AM, Krzysztof Kozlowski wrote: > On Wed, Jan 04, 2017 at 09:34:34PM +0900, Jaehoon Chung wrote: >> This patch is for using PHY generic framework. >> To maintain backward compatibility, check whether phy is supported or >> not with 'using_phy'. >> >> And if someone use the old dt-file, display the "deprecated" message. >> But it's still working fine with it. > > This needs improvements. How about: > "Switch the pci-exynos driver to generic PHY framework. At the same time > backward compatibility is preserved: warning will be printed for old > DTB. Thanks for comments. Will describe the commit-msg in more detail. Best Regards, Jaehoon Chung > > Acked-by: Krzysztof Kozlowski > > Best regards, > Krzysztof > >> >> Signed-off-by: Jaehoon Chung >> --- >> Changelog on V2: >> - This patch is split from previous PATCH[1/4] >> - Maintain the backward compatibility >> - Adds 'using_phy' for cheching whether phy framework is used or not >> - Adds 'DEPRECATED' message for old dt-binding way >> >> drivers/pci/host/pci-exynos.c | 61 +++++++++++++++++++++++++++++++++++-------- >> 1 file changed, 50 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c >> index feed0fd..34f2eed 100644 >> --- a/drivers/pci/host/pci-exynos.c >> +++ b/drivers/pci/host/pci-exynos.c >> @@ -21,6 +21,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -110,6 +111,10 @@ struct exynos_pcie { >> struct exynos_pcie_clk_res *clk_res; >> const struct exynos_pcie_ops *ops; >> int reset_gpio; >> + >> + /* For Generic PHY Framework */ >> + bool using_phy; >> + struct phy *phy; >> }; >> >> struct exynos_pcie_ops { >> @@ -135,6 +140,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev, >> if (IS_ERR(ep->mem_res->elbi_base)) >> return PTR_ERR(ep->mem_res->elbi_base); >> >> + /* If using the PHY framework, doesn't need to get other resource */ >> + if (ep->using_phy) >> + return 0; >> + >> res = platform_get_resource(pdev, IORESOURCE_MEM, 1); >> ep->mem_res->phy_base = devm_ioremap_resource(dev, res); >> if (IS_ERR(ep->mem_res->phy_base)) >> @@ -396,17 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie) >> } >> >> exynos_pcie_assert_core_reset(exynos_pcie); >> - exynos_pcie_assert_phy_reset(exynos_pcie); >> - exynos_pcie_deassert_phy_reset(exynos_pcie); >> - exynos_pcie_power_on_phy(exynos_pcie); >> - exynos_pcie_init_phy(exynos_pcie); >> - >> - /* pulse for common reset */ >> - exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1, >> - PCIE_PHY_COMMON_RESET); >> - udelay(500); >> - exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0, >> - PCIE_PHY_COMMON_RESET); >> + >> + if (exynos_pcie->using_phy) { >> + phy_reset(exynos_pcie->phy); >> + >> + exynos_pcie_writel(exynos_pcie->mem_res->elbi_base, 1, >> + PCIE_PWR_RESET); >> + >> + phy_power_on(exynos_pcie->phy); >> + phy_init(exynos_pcie->phy); >> + } else { >> + exynos_pcie_assert_phy_reset(exynos_pcie); >> + exynos_pcie_deassert_phy_reset(exynos_pcie); >> + exynos_pcie_power_on_phy(exynos_pcie); >> + exynos_pcie_init_phy(exynos_pcie); >> + >> + /* pulse for common reset */ >> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1, >> + PCIE_PHY_COMMON_RESET); >> + udelay(500); >> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0, >> + PCIE_PHY_COMMON_RESET); >> + } >> >> exynos_pcie_deassert_core_reset(exynos_pcie); >> dw_pcie_setup_rc(pp); >> @@ -420,6 +440,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie) >> if (!dw_pcie_wait_for_link(pp)) >> return 0; >> >> + if (exynos_pcie->using_phy) { >> + phy_power_off(exynos_pcie->phy); >> + return -ETIMEDOUT; >> + } >> + >> while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base, >> PCIE_PHY_PLL_LOCKED) == 0) { >> val = exynos_pcie_readl(exynos_pcie->mem_res->block_base, >> @@ -633,6 +658,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) >> >> exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); >> >> + /* Assume that controller doesn't use the PHY framework */ >> + exynos_pcie->using_phy = false; >> + >> + exynos_pcie->phy = devm_of_phy_get(dev, np, NULL); >> + if (IS_ERR(exynos_pcie->phy)) { >> + if (PTR_ERR(exynos_pcie->phy) == -EPROBE_DEFER) >> + return PTR_ERR(exynos_pcie->phy); >> + dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n"); >> + } else >> + exynos_pcie->using_phy = true; >> + >> if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) { >> ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie); >> if (ret) >> @@ -657,6 +693,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) >> return 0; >> >> fail_probe: >> + if (exynos_pcie->using_phy) >> + phy_exit(exynos_pcie->phy); >> + >> if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources) >> exynos_pcie->ops->deinit_clk_resources(exynos_pcie); >> return ret; >> -- >> 2.10.2 >> > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > >