From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B95BCA9EAF for ; Fri, 25 Oct 2019 02:56:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7063B21D7B for ; Fri, 25 Oct 2019 02:56:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391226AbfJYC4Z (ORCPT ); Thu, 24 Oct 2019 22:56:25 -0400 Received: from mga04.intel.com ([192.55.52.120]:23135 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389230AbfJYC4Z (ORCPT ); Thu, 24 Oct 2019 22:56:25 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Oct 2019 19:56:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,227,1569308400"; d="scan'208";a="197908623" Received: from allen-box.sh.intel.com (HELO [10.239.159.136]) ([10.239.159.136]) by fmsmga007.fm.intel.com with ESMTP; 24 Oct 2019 19:56:22 -0700 Cc: baolu.lu@linux.intel.com, Yi Liu , "Tian, Kevin" , Raj Ashok , Christoph Hellwig , Jonathan Cameron , Eric Auger Subject: Re: [PATCH v7 01/11] iommu/vt-d: Cache virtual command capability register To: Jacob Pan , iommu@lists.linux-foundation.org, LKML , Joerg Roedel , David Woodhouse , Alex Williamson , Jean-Philippe Brucker References: <1571946904-86776-1-git-send-email-jacob.jun.pan@linux.intel.com> <1571946904-86776-2-git-send-email-jacob.jun.pan@linux.intel.com> From: Lu Baolu Message-ID: <6d141036-2160-45de-754f-9b146dac541e@linux.intel.com> Date: Fri, 25 Oct 2019 10:53:49 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <1571946904-86776-2-git-send-email-jacob.jun.pan@linux.intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 10/25/19 3:54 AM, Jacob Pan wrote: > Virtual command registers are used in the guest only, to prevent > vmexit cost, we cache the capability and store it during initialization. > > Signed-off-by: Jacob Pan This patch looks good to me. Reviewed-by: Lu Baolu Best regards, baolu > --- > drivers/iommu/dmar.c | 1 + > include/linux/intel-iommu.h | 4 ++++ > 2 files changed, 5 insertions(+) > > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c > index eecd6a421667..49bb7d76e646 100644 > --- a/drivers/iommu/dmar.c > +++ b/drivers/iommu/dmar.c > @@ -950,6 +950,7 @@ static int map_iommu(struct intel_iommu *iommu, u64 phys_addr) > warn_invalid_dmar(phys_addr, " returns all ones"); > goto unmap; > } > + iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG); > > /* the registers might be more than one page */ > map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), > diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h > index ed11ef594378..2e1bed9b7eef 100644 > --- a/include/linux/intel-iommu.h > +++ b/include/linux/intel-iommu.h > @@ -186,6 +186,9 @@ > #define ecap_max_handle_mask(e) ((e >> 20) & 0xf) > #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */ > > +/* Virtual command interface capabilities */ > +#define vccap_pasid(v) ((v & DMA_VCS_PAS)) /* PASID allocation */ > + > /* IOTLB_REG */ > #define DMA_TLB_FLUSH_GRANU_OFFSET 60 > #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) > @@ -520,6 +523,7 @@ struct intel_iommu { > u64 reg_size; /* size of hw register set */ > u64 cap; > u64 ecap; > + u64 vccap; > u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ > raw_spinlock_t register_lock; /* protect register handling */ > int seq_id; /* sequence id of the iommu */ >